參數(shù)資料
型號: MC14553
廠商: Motorola, Inc.
英文描述: Single Channel (3.0V) SVS with /MR in 5/SOT23 5-SOT-23 -40 to 85
中文描述: 3位BCD碼計數(shù)器
文件頁數(shù): 1/8頁
文件大?。?/td> 231K
代理商: MC14553
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
1
MC14553B
The MC14553B 3–digit BCD counter consists of 3 negative edge triggered
BCD counters that are cascaded synchronously. A quad latch at the output
of each counter permits storage of any given count. The information is then
time division multiplexed, providing one BCD number or digit at a time. Digit
select outputs provide display control. All outputs are TTL compatible.
An on–chip oscillator provides the low–frequency scanning clock which
drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays, digital
panel meters, and as a building block for general logic applications.
TTL Compatible Outputs
On–Chip Oscillator
Cascadable
Clock Disable Input
Pulse Shaping Permits Very Slow Rise Times on Input Clock
Output Latches
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
Iin
Iout
PD
Tstg
TL
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
DC Supply Voltage
– 0.5 to + 18.0
V
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
±
10
V
Input Current (DC or Transient), per Pin
mA
Output Current (DC or Transient), per Pin
+ 20
mA
Power Dissipation, per Package
500
mW
Storage Temperature
– 65 to + 150
C
Lead Temperature (8–Second Soldering)
260
C
TRUTH TABLE
Inputs
Outputs
Master
Reset
Clock
Disable
LE
0
0
0
0
0
0
0
0
1
0
0
1
0
0
X
0
0
X
No Change
Advance
No Change
Advance
No Change
No Change
Latched
Latched
X
1
1
0
X
X
X
X
X
X
X
1
0
Q0 = Q1 = Q2 = Q3 = 0
X = Don’t Care
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
BLOCK DIAGRAM
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
VDD.
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
12
10
11
13
9
7
6
5
14
2
1
15
VDD = PIN 16
VSS = PIN 8
4
3
CLOCK
LE
DIS
MR
Q0
Q1
Q2
Q3
O.F.
DS1
DS2
DS3
CIA
CIB
相關PDF資料
PDF描述
MC14553B Single Channel (1.5V) SVS with /MR in 5/SOT23 5-SOT-23 -40 to 85
MC14554B Single Channel (1.8V) SVS with /MR in 5/SOT23 5-SOT-23 -40 to 85
MC14554 2-Bit by 2-Bit Parallel Binary Multiplier
MC145554 Single Channel (1.2V) SVS w/ Watchdog and /MR in 5/SOT23 5-SOT-23 -40 to 85
MC14555 Dual Binary to 1-of-4 Decoder/Demultiplexer
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