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參數(shù)資料
| 型號： | MC14544BCP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | BCD-to-Seven Segment Latch/Decoder/Driver for Liquid Crystals |
| 中文描述： | 4000/14000/40000 SERIES, SEVEN SEGMENT DECODER/DRIVER, CONFIGURABLE OUTPUT, PDIP18 |
| 封裝： | PLASTIC, DIP-18 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 263K |
| 代理商： | MC14544BCP |
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
1
MC14544B
"
"
! #
CMOS MSI (Low–Power Complementary MOS)
The MC14544B BCD–to–seven segment latch/decoder/driver is designed
for use with liquid crystal readouts, and is constructed with complementary
MOS (CMOS) enhancement mode devices. The circuit provides the
functions of a 4–bit storage latch and an 8421 BCD–to–seven segment
decoder and driver. The device has the capability to invert the logic levels of
the output combination. The phase (Ph), blanking (BI), and latch disable (LD)
inputs are used to reverse the truth table phase, blank the display, and store
a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is
applied to the Ph input of the circuit and the electrically common backplane
of the display. The outputs of the circuit are connected directly to the
segments of the LC readout. The Ripple Blanking Input (RBI) and the Ripple
Blanking Output (RBO) can be used to suppress either leading or trailing
zeroes.
For other types of readouts, such as light–emitting diode (LED),
incandescent, gas discharge, and fluorescent readouts, connection dia-
grams are given on this data sheet.
Applications include instrument (e.g., counter, DVM etc.) display driver,
computer/calculator display driver, cockpit display driver, and various clock,
watch, and timer uses.
Latch Storage of Code
Blanking Input
Readout Blanking on All Illegal Input Combinations
Direct LED (Common Anode or Cathode) Driving Capability
Supply Voltage Range = 3.0 V to 18 V
Capability for Suppression of Non–significant zero
Capable of Driving Two Low–power TTL Loads, One Low–power
DC Supply Voltage
VDD
Vin
Iin
TA
PD
Tstg
IOHmax
IOLmax
POHmax
POLmax
– 0.5 to + 18
V
Input Voltage, All Inputs
– 0.5 to VDD + 0.5
±
10
V
DC Input Current per Pin
mAdc
Operating Temperature Range
– 55 to + 125
C
Power Dissipation, per Package
500
mW
Storage Temperature Range
– 65 to + 150
C
Maximum Continuous Output Drive
Current (Source or Sink) per Output
10
mAdc
Maximum Continuous Output Power*
(Source or Sink) per Output
70
mW
* POHmax = IOH (VOH – VDD) and POLmax = IOL (VOL – VSS)
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 726
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
Plastic
Ceramic
TA = – 55
°
to 125
°
C for all packages.
P SUFFIX
PLASTIC
CASE 707
PIN ASSIGNMENT
A
B
C
LD
VSS
RBO
BI
PH
D
e
g
f
VDD
RBI
a
b
c
d
14
15
16
17
18
10
11
12
13
5
4
3
2
1
9
8
7
6
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
VDD.
0
1
2
3
4
5
6
7
8
9
DISPLAY
a
b
c
d
e
f
g
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