MASTER SWITCHING CHARACTERISTICS (VDD = 5 V ±10%, TA = –40° to 85°C, CL = 50 pF)" />
參數(shù)資料
型號： MC145423EJ
廠商： Freescale Semiconductor
文件頁數(shù)： 10/15頁
文件大小： 0K
描述： IC TXRX UDLT/ISDN 28-TSSOP
標(biāo)準(zhǔn)包裝： 50
類型： 收發(fā)器
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 管件
MC145423
TELECOMMUNICATIONS
6
MASTER SWITCHING CHARACTERISTICS (VDD = 5 V ±10%, TA = –40° to 85°C, CL = 50 pF)
Parameter
Figure
No.
Symbol
Min
Max
Unit
Input Rise Time: All Digital Inputs
tr
—2
s
Input Fall Time: All Digital Inputs
tf
—2
s
Pulse Width:
TDC, RDC, RE1, RE2, MSI, SDCLK (UDLT-2)
tp
90
—
ns
CCI Duty Cycle
tw2(H,L)
45
55
%
Propagation Delay:
MSI to SDO1, SDO2, VD (PD = VDD)
TDC to Tx
tPLH,
tPHL
—
50
ns
MSI, TE1, TE2, RE1, RE2 to TDC-RDC Setup Time
tsu3
20
—
ns
TDC-RDC to MSI, TE1, TE2, RE1, RE2, Hold Time
th5
50
—
ns
Rx to TDC-RDC Setup Time
tsu5
30
—
ns
Rx to TDC-RDC Hold Time
th1
30
—
ns
SDI1, SDI2 to MSI Setup Time
tsu2
30
—
ns
SDI1, SDI2 to MSI Hold Time
th2
30
—
ns
MSI Rising Edge to First SDCLK Falling Edge
(UDLT-2 Only)
tP1LH
—50
ns
TE Rising Edge to First Tx Data Bit Valid
tsu6
—50
ns
TDC-RDC Rising Edge to Tx Data Bits 2 – 8 Valid
tsu7
—50
ns
TE1,TE2 Falling Edge to Tx High Impedance
tdly
—70
ns
SDCLK Rising Edge to SDO1, SDO2 Bit Valid
(UDLT-2 Only)
tsu8
—
135
ns
SDI1, SDI2 Data Setup (Data Valid Before SDCLK
Falling Edge) (UDLT-2 Only)
tsu9
50
—
ns
SDI1, SDI2 Data Hold (Data Valid After SDCLK
Falling Edge) (UDLT-2 Only)
th3
20
—
ns
PD, LB Setup (PD, LB Valid Before MSI Rising Edge)
tsu10
50
—
ns
PD, LB Hold (PD, LB Valid After MSI Rising Edge)
th4
20
—
ns
TELECOMMUNICATIONS
7
MC145423
SLAVE SWITCHING CHARACTERISTICS (VDD = 5 V ±10%, TA = –40° to 85°C, CL = 50 pF)
Parameter
Figure
No.
Symbol
Min
Max
Unit
Input Rise Time: All Digital Inputs
tr
—2
s
Input Fall Time: All Digital Inputs
tf
—2
s
Clock Output Pulse Width: BCLK
tw(H,L)
3.66
4.15
s
Crystal Frequency
fx1
4.086
4.1
MHz
Propagation Delay Times:
EN1, EN2, TE1 Rising to BCLK (TONE = VDD)
EN1, EN2, TE1 Rising to BCLK (TONE = VSS)
BCLK to EN1, EN2, TE1 Falling
RE1 Rising to BCLK (UDLT-1)
RE1 Falling to BCLK (TONE = VDD) (UDLT-1)
RE1 Falling to BCLK (TONE = VSS) (UDLT-1)
BCLK to Tx
TE1,TE2 to SDO1, SDO2
tp1
tp2
tp3
tp4
tp5
tp6
–50
300
—
–50
300
—
175
400
20
50
400
50
ns
Rx to BCLK Setup Time
tsu5
30
—
ns
Rx to BCLK Hold Time
th1
30
—
ns
SDI1, SDI2 to TE Setup Time
tsu6
30
—
ns
SDI1, SDI2 to TE Hold Time
th2
30
—
ns
EN1, EN2 Rising Edge to DCLK Rising Edge (UDLT-2)
tPHL
—
±30
ns
EN1, EN2 Rising Edge to First Tx Data Bit Valid
tdly1
—30
ns
BCLK Rising Edge to Tx Data Bits 2 – 8 Valid
tsu7
—
–40
ns
DCLK Pulse Width High (UDLT-2)
tw(H)
31
31.5
s
DCLK Pulse Width Low (UDLT-2)
tw(L)
31
31.5
s
DCLK Rising Edge to SDO1, SDO2 (UDLT-2)
tdly2
—30
ns
SDI1, SDI2 Setup (SDI1, SDI2 Valid Before DCLK
Falling Edge) (UDLT-2)
tsu9
10
—
ns
SDI1, SDI2 Hold (SDI1, SDI2 Valid After DCLK
Falling Edge) (UDLT-2)
th3
—30
ns
EN1, TE1 Rising Edge to VD Valid
tdly3
—30
ns
SE PIN TIMING
Parameter
Figure
No.
Symbol
Min
Max
Unit
LB, PD Hold
(LB, PD Valid After SE Falling Edge)
th
10
—
ns
SDO1, SDO2, VD High Impedance After SE Falling Edge
tdly1
—40
ns
SDO1, SDO2, VD Valid After SE Rising Edge
tdly2
30
—
ns
LB, PD Setup
(LB, PD Valid Before SE Rising Edge)
tsu
25
—
ns
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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