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參數(shù)資料
| 型號： | MC145421 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Universal Digital-Loop Transceiver2(通用數(shù)字回路收發(fā)器) |
| 中文描述： | DATACOM, DIGITAL SLIC, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 268K |
| 代理商： | MC145421 |
MC145421
MC145425
4
MOTOROLA
ABSOLUTE MAXIMUM RATINGS
(Voltage Referenced to VSS)
Rating
Symbol
Value
Unit
DC Supply Voltage
VDD – VSS
V
– 0.5 to 6.5
V
Voltage Any Pin to VSS
DC Current, Any Pin (Excluding VDD,
VSS)
– 0.5 to VDD + 0.5
±
10
V
I
mA
Operating Temperature
TA
Tstg
– 40 to + 85
°
C
Storage Temperature
– 85 to + 150
°
C
RECOMMENDED OPERATING CONDITIONS
(TA = – 40 to + 85
°
C
)
Parameter
Pins
Min
Typ
Max
Unit
DC Supply Voltage
VDD
MSI
4.5
5.0
5.5
V
Frame Rate MC145421 (See Note)
—
8.0
—
kHz
MC145421/25 Frame Slip Rate (See Note)
—
—
—
0.25
%
CCI Clock Frequency
—
—
8.192
8.29
MHz
TDC/RDC Data Clocks (for Master)
—
0.128
—
4.1
MHz
DCLK
—
0.016
—
4.1
MHz
Modulation Baud Rate (CCI/16)
LO1, LO2
—
512
—
kHz
NOTE: The slave’s crystal frequency divided by 1024 must equal the master’s MSI frequency
±
0.25% for optimum operation. Also, the
8.192 MHz input at the master divided by 1024 must be within 0.048% of the master’s 8 kHz MSI clock frequency.
DIGITAL CHARACTERISTICS
(VDD = 5 V, TA = – 40 to + 85
°
C)
Parameter
Min
Max
Unit
Input High Level
3.5
—
V
Input Low Level
—
1.5
V
Input Current, VDD
Input Current (Digital Pins)
—
15
mA
—
5
μ
A
Input Capacitance
—
10
pF
Output High Current (Except Tx on Master and Slave, and PD on the Slave)
VOH = 2.5
VOH = 4.6
VOH = 2.5
VOH = 4.6
VOH = 2.5
VOL = 0.4
VOL = 0.8
VOL = 0.4
VOL = 0.8
VOL = 0.4
– 1.7
– 0.36
—
—
mA
Tx Output High Current
– 3.4
– 0.7
—
—
mA
PD (Slave) Output High Current (See Note)
—
– 90
μ
A
Output Low Current (Except Tx on Master and Slave, and PD on Slave)
0.36
0.8
—
—
mA
Tx Output Low Current
1.7
3.5
—
—
mA
PD (Slave) Output Low Current (See Note)
30
60
μ
A
k
μ
A
μ
A
Tx Three–State Impedance
100
—
XTL Output High Current
VOH = 4.6
VOH = 0.4
—
– 450
XTL Output Low Current
450
—
NOTE: To overdrive PD from a low level to 3.5 V, or a high level to 1.5 V requires a minimum of
±
800
μ
A drive capability.
ANALOG CHARACTERISTICS
(VDD = 5 V, TA = 0 to 70
°
C)
Parameter
Min
Max
Unit
Modulation Differential Amplitude RL = 880
(LO1 – LO2)
4.6
—
Vpeak
Modulation Differential DC Offset
—
40
mV
Vref Voltage (Typically 9/20 (VDD – VSS))
PCM Tone Level
2.0
2.5
V
– 22
– 18
dBm
Demodulator Input Amplitude
50
—
mVpeak
Demodulator Input Impedance (LI to Vref)
75
300
k
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken to
avoid applications of any voltage higher than
maximum rated voltages to this high imped-
ance circuit. For proper operation it is recom-
mended that Vin and Vout be constrained to
the range VSS
≤
(Vin or Vout)
≤
VDD. Reliability
of operation is enhanced if unused inputs are
tied to an appropriate logic voltage level (e.g.,
either VSS or VDD).
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