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參數(shù)資料
| 型號(hào)： | MC14536BFL2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | 1 TIMER(S), PROGRAMMABLE TIMER, PDSO16 |
| 封裝： | EIAJ, PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 18/18頁 |
| 文件大?。?/td> | 328K |
| 代理商： | MC14536BFL2 |
MC14536B
http://onsemi.com
9
Figure 6. Power Dissipation Test
Circuit and Waveform
Figure 7. Switching Time Test Circuit and Waveforms
VDD
0.01
F
CERAMIC
500
F
ID
CL
VSS
PULSE
GENERATOR
SET
RESET
8–BYPASS
IN1
C INH
MONO IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
20 ns
90%
10%
50%
DUTY CYCLE
PULSE
GENERATOR
SET
RESET
8–BYPASS
IN1
C INH
MONO IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
CL
VSS
VDD
20 ns
50%
IN1
tWL
tWH
50%
tPHL
90%
10%
tPLH
tTLH
tTHL
OUT
FUNCTIONAL TEST SEQUENCE
Test function (Figure 8) has been included for the
reduction of test time required to exercise all 24 counter
stages. This test function divides the counter into three
8–stage sections and 255 counts are loaded in each of the
8–stage sections in parallel. All flip–flops are now at a “1”.
The counter is now returned to the normal 24–stages in
series configuration. One more pulse is entered into In1
which will cause the counter to ripple from an all “1” state
to an all “0” state.
Figure 8. Functional Test Circuit
VDD
VSS
PULSE
GENERATOR
SET
RESET
8–BYPASS
IN1
C INH
MONO IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
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