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MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
1
MC14522B MC14526B
The MC14522B BCD counter and the MC14526B binary counter are
constructed with MOS P–channel and N–channel enhancement mode
devices in a monolithic structure.
These devices are presettable, cascadable, synchronous down counters
with a decoded “0” state output for divide–by–N applications. In single stage
applications the “0” output is applied to the Preset Enable input. The
Cascade Feedback input allows cascade divide–by–N operation with no
additional gates required. The Inhibit input allows disabling of the pulse
counting function. Inhibit may also be used as a negative edge clock.
These complementary MOS counters can be used in frequency synthesiz-
ers, phase–locked loops, and other frequency division applications requiring
low power dissipation and/or high noise immunity.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge–Clocked Design — Incremented on Positive Transition of
Clock or Negative Transition of Inhibit
Asynchronous Preset Enable
Symbol
Parameter
VDD
DC Supply Voltage
Vin, Vout
Input or Output Voltage (DC or Transient)
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
Value
Unit
– 0.5 to + 18.0
V
– 0.5 to VDD + 0.5
±
10
V
mA
PD
Tstg
TL
Power Dissipation, per Package
500
mW
Storage Temperature
– 65 to + 150
C
Lead Temperature (8–Second Soldering)
260
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
FUNCTION TABLE
Inputs
Preset
Enable
Feedback
Output
Function
Clock
X
X
X
Reset
H
H
H
Inhibit
X
X
X
Cascade
“0”
L
H
H
Resulting
L
H
X
L
L
H
Asynchronous reset*
Asynchronous reset
Asynchronous reset
X
L
X
H
X
L
Asynchronous preset
L
L
L
H
L
L
X
X
L
L
Decrement inhibited
Decrement inhibited
L
L
L
L
L
L
L
L
L
L
L
L
L
Decrement**
H
L
No change** (inactive edge)
No change** (inactive edge)
Decrement**
H
L
L
L
L
X = Don’t Care
NOTES:
*Output “0” is low when reset goes high only it PE and CF are low.
**Output “0” is high when reset is low, only if CF is high and count is 0000.
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
VDD.
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
“0”
CF
P2
Q2
VDD
Q1
RESET
P1
INHIBIT
PE
P3
Q3
VSS
Q0
CLOCK
P0