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參數(shù)資料
| 型號(hào)： | MC14518BDW |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 0K |
| 描述： | IC COUNTER DUAL BCD 16-SOIC |
| 產(chǎn)品變化通告： | LTB Notification 03/Jan/2008 |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 系列： | 4000B |
| 邏輯類型： | BCD 計(jì)數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 2 |
| 每個(gè)元件的位元數(shù)： | 4 |
| 復(fù)位： | 異步 |
| 計(jì)時(shí)： | 同步 |
| 計(jì)數(shù)速率： | 8MHz |
| 觸發(fā)器類型： | 正，負(fù) |
| 電源電壓： | 3 V ~ 18 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
Semiconductor Components Industries, LLC, 2013
May, 2013 Rev. 7
1
Publication Order Number:
MC14518B/D
MC14518B, MC14520B
Dual Up Counters
The MC14518B dual BCD counter and the MC14520B dual binary
counter are constructed with MOS Pchannel and Nchannel
enhancement mode devices in a single monolithic structure. Each
consists of two identical, independent, internally synchronous 4stage
counters. The counter stages are type D flipflops, with interchangeable
Clock and Enable lines for incrementing on either the positivegoing or
negativegoing transition as required when cascading multiple stages.
Each counter can be cleared by applying a high level on the Reset line.
In addition, the MC14518B will count out of all undefined states within
two clock periods. These complementary MOS up counters find
primary use in multistage synchronous or ripple counting applications
requiring low power dissipation and/or high noise immunity.
Features
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Internal and External Speeds
Logic EdgeClocked Design — Incremented on Positive Transition
of Clock or Negative Transition on Enable
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 2.)
500
mW
TA
Operating Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout
should be constrained to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
xx
= 18 or 20
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= PbFree Indicator
MARKING
DIAGRAMS
1
16
PDIP16
P SUFFIX
CASE 648
MC145xxBCP
AWLYYWWG
SO16 WB
DW SUFFIX
CASE 751G
1
16
145xxB
AWLYYWWG
SOEIAJ16
F SUFFIX
CASE 966
1
16
MC145xxB
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
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