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參數(shù)資料
| 型號： | MC145162P |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | 60 MHz and 85 MHz Universal Programmable Dual PLL Frequency Synthesizers |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 60 MHz, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 223K |
| 代理商： | MC145162P |
MC145162
MC145162–1
8
MOTOROLA
Figure 8. Programming Format of the Control Register
NOTE: ENB must be high during the serial transfer.
ENB
CONTROL REGISTER IDENTIFIER = 1
REF PD
ENABLE
RxPD
ENABLE
TxPD
ENABLE
1
0
TEST
BIT
AUX
DATA
SELECT
CONTROL REGISTER DATA
Din
REF
OUT
3/
MSB
LSB
CLK
4
Table 1. Control Register Function Bits Description
Test Bit
Set to 1 for Tx/Rx channel counter test mode
Set to 0 for normal application
Aux Data Select
Set to 1 for both ADin and Din pins inputting the transmit 16–bits data and receive 16–bits data
respectively.
Set to 0 for normal application interfacing with MCU serial peripheral interface. Does not use ADin pin;
tie ADin to VSS.
REFout
3/
4
If set to 1, REFout output frequency is equal to OSCout
If set to 0, REFout output is OSCout
3.
4.
TxPD Enable
If set to 1, the transmit counter, transmit phase detector, and the associated circuitry is in power–
down mode.
Tx PS/fTx is set “High”.
RxPD Enable
If set to 1, the receive counter, receive phase detector, and the associated circuitry is in power–
down mode.
Rx PS/fRx is set “High”.
Ref PD Enable
If set to 1, both 12–bit and 14–bit reference frequency counters are in power–down mode.
Table 2. Control Register Power Down Bits Function
TxPD
Enable
RxPD
Enable
REF PD
Enable
Tx–Channel Counter
Rx–Channel Counter
Reference
Frequency Counter
0
0
0
—
—
—
0
0
1
—
—
Power Down
0
1
0
—
Power Down
—
0
1
1
—
Power Down
Power Down
1
0
0
Power Down
—
—
1
0
1
Power Down
—
Power Down
1
1
0
Power Down
Power Down
—
1
1
1
Power Down
Power Down
Power Down
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