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參數(shù)資料
| 型號(hào)： | MC145159VF1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | Complementary Dual High-Speed MOSFET Drivers with Internal Regulator 8-SOIC |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 223K |
| 代理商： | MC145159VF1 |
MC145159–1
8
MOTOROLA
DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a ref-
erence frequency to Motorola’s CMOS frequency synthe-
sizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscilla-
tors provide very stable reference frequencies. An oscillator
capable of sinking and sourcing 50
μ
A at CMOS logic levels
may be direct or dc coupled to OSCin. In general, the highest
frequency capability is obtained utilizing a direct coupled
square wave having a rail–to–rail (VDD to VSS) voltage
swing. If the oscillator does not have CMOS logic levels on
the outputs, capacitive or ac coupling to OSCin may be used.
OSCout, an unbuffered output, should be left floating.
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem Elec-
tronic Engineers Master Catalog,the Gold Book,or similar
publications.
Design an Off–Chip Reference
The user may design an off–chip crystal oscillator using
ICs specifically developed for crystal oscillator applications,
such as the MC12061 MECL device. The reference signal
from the MECL device is ac coupled to OSCin. For large am-
plitude signals (standard CMOS logic levels), dc coupling is
used. OSCout, an unbuffered output, should be left floating.
In general, the highest frequency capability is obtained with a
direct–coupled square wave having rail–to–rail voltage
swing.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an ap-
propriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 10.
For VDD = 5 V, the crystal should be specified for a loading
capacitance, CL, which does not exceed 32 pF for frequen-
cies to approximately 8 MHz, 20 pF for frequencies in the
area of 8 to 15 MHz, and 10 pF for higher frequencies. These
are guidelines that provide a reasonable compromise be-
tween IC capacitance, drive capability, swamping variations
in stray and IC input/output capacitance, and realistic CL val-
ues. Assuming R1 = 0
. the shunt load capacitance, CL,
presented across the crystal can be estimated to be:
CinCout
Cin + Cout
where
Cin= 5 pF (see Figure 11)
Cout= 6 pF (see Figure 11)
Ca= 1 pF (see Figure 11)
C1 and C2 = external capacitors (see Figure 10)
Cstray= the total equivalent external circuit stray
capacitance appearing across the
crystal terminals
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated com-
ponents must be located as close as possible to the OSCin
and OSCout pins to minimize distortion, stray capacitance,
CL =
+ Ca + Cstray +C1
C2
C1 + C2
stray inductance, and start–up stabilization time. Circuit stray
capacitance can also be handled by adding the appropriate
stray value to the values for Cin and Cout. For this approach,
the term Cstray becomes zero in the above expression for CL.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 12. The maximum drive level specified
by the crystal manufacturer represents the maximum stress
that a crystal can withstand without damaging or excessive
shift in operating frequency. R1 in Figure 10 limits the drive
level. The use of R1 is not necessary in most cases.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a func-
tion of voltage at OSCout. (Care should be taken to minimize
loading.) The frequency should increase very slightly as the
dc supply voltage is increased. An overdriven crystal will
decrease in frequency or become unstable with an increase
in supply voltage. The operating supply voltage must be
reduced or R1 must be increased in value if the overdriven
condition exists. The user should note that the oscillator
start–up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have devel-
oped expertise in CMOS oscillator design with crystals. Dis-
cussions with such manufacturers can prove very helpful.
See Table 1.
Figure 10. Pierce Crystal Oscillator Circuit
* May be deleted in certain cases. See text.
Figure 11. Parasitic Capacitances of the
Amplifier and Cstray
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
Figure 12. Equivalent Crystal Networks
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