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參數(shù)資料
| 型號： | MC145157P2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | Parallel-Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 22 MHz, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 718K |
| 代理商： | MC145157P2 |
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MC145151–2 through MC145158–2
10
MOTOROLA
14 x 8 ROM REFERENCE DECODER
14–BIT
÷
N COUNTER
φ
V
φ
R
14–BIT
÷
R COUNTER
LATCH
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT
LD
PDout
fin
VDD
OSCin
OSCout
ENB
14
14
SW2
SW1
fR
fV
LATCH
14–BIT SHIFT REGISTER
DATA
2–BIT SHIFT
REGISTER
CLK
14
REFout
MC145155–2 BLOCK DIAGRAM
RA2
RA1
RA0
PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (PDIP – Pin 9, SOG – Pin 10)
Input to the
÷
N portion of the synthesizer. fin is typically
derived from loop VCO and is ac coupled into the device. For
larger amplitude signals (standard CMOS logic levels) dc
coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (PDIP – Pins 18, 1, 2;
SOG – Pins 20, 1, 2)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider, as
defined by the table below:
Reference Address Code
Total
Value
RA2
RA1
RA0
Divide
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
512
1024
2048
3668
4096
6144
8192
CLK, DATA
Shift Register Clock, Serial Data Inputs
(PDIP – Pins 10, 11; SOG – Pins 11, 12)
Each low–to–high transition clocks one bit into the on–chip
16–bit shift register. The Data input provides programming
information for the 14–bit
÷
N counter and the two switch sig-
nals SW1 and SW2. The entry format is as follows:
S
S
N
÷
N
÷
÷
N COUNTER BITS
LAST DATA BIT IN (BIT NO. 16)
FIRST DATA BIT IN (BIT NO. 1)
ENB
Latch Enable Input (PDIP – Pin 12, SOG – Pin 13)
When high (1), ENB transfers the contents of the shift reg-
ister into the latches, and to the programmable counter in-
puts, and the switch outputs SW1 and SW2. When low (0),
ENB inhibits the above action and thus allows changes to be
made in the shift register data without affecting the counter
programming and switch outputs. An on–chip pull–up esta-
blishes a continuously high level for ENB when no external
signal is applied. ENB is normally low and is pulsed high to
transfer data to the latches.
OSCin, OSCout
Reference Oscillator Input/Output (PDIP – Pins 17, 16;
SOG – Pins 19, 18)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSCin to ground and OSCout to ground.
OSCin may also serve as the input for an externally–gener-
ated reference signal. This signal is typically ac coupled to
OSCin, but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSCout.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145158-2 | 制造商:Motorola Inc 功能描述: |
| MC145158DW2 | 功能描述:IC SER-IN PLL FREQ SYNTH 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC145158DW2R2 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MC145159FN1R2 | 制造商:Motorola Inc 功能描述: |
| MC145159P1 | 制造商:Motorola Inc 功能描述: |
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