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參數(shù)資料
| 型號： | MC145157DW2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | Parallel-Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 22 MHz, PDSO16 |
| 封裝： | SOG-16 |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 718K |
| 代理商： | MC145157DW2 |
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MC145151–2 through MC145158–2
22
MOTOROLA
OUTPUT PINS
PDout
Phase Detector A Output (Pin 5)
This single–ended (three–state) phase detector output
produces a loop–error signal that is used with a loop filter to
control a VCO.
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High–Imped-
ance State
φ
R,
φ
V
Phase Detector B Outputs (Pins 16, 15)
Double–ended phase detector outputs. These outputs can
be combined externally for a loop–error signal. A single–
ended output is also available for this purpose (see
PDout
).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by
φ
V pulsing low.
φ
R remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by
φ
R pulsing low.
φ
V remains essentially high.
If the frequency of fV = fR and both are in phase, then both
φ
V and
φ
R remain high except for a small minimum time
period when both pulse low in phase.
MC
Dual–Modulus Prescale Control Output (Pin 12)
This output generates a signal by the on–chip control logic
circuitry for controlling an external dual–modulus prescaler.
The MC level is low at the beginning of a count cycle and
remains low until the
÷
A counter has counted down from its
programmed value. At this time, MC goes high and remains
high until the
÷
N counter has counted the rest of the way
down from its programmed value (N – A additional counts
since both
÷
N and
÷
A are counting down during the first por-
tion of the cycle). MC is then set back low, the counters pre-
set to their respective programmed values, and the above
sequence repeated. This provides for a total programmable
divide value (NT) = N P + A where P and P + 1 represent the
dual–modulus prescaler divide values respectively for high
and low modulus control levels, N the number programmed
into the
÷
N counter, and A the number programmed into the
÷
A counter. Note that when a prescaler is needed, the dual–
modulus version offers a distinct advantage. The dual–
modulus prescaler allows a higher reference frequency at
the phase detector input, increasing system performance ca-
pability, and simplifying the loop filter design.
fR, fV
R Counter Output, N Counter Output (Pins 13, 3)
Buffered, divided reference and fin frequency outputs. The
fR and fV outputs are connected internally to the
÷
R and
÷
N counter outputs respectively, allowing the counters to be
used independently, as well as monitoring the phase detector
inputs.
LD
Lock Detector Output (Pin 7)
This output is essentially at a high level when the loop is
locked (fR, fV of same phase and frequency), and pulses low
when loop is out of lock.
REFout
Buffered Reference Oscillator Output (Pin 14)
This output can be used as a second local oscillator, refer-
ence oscillator to another frequency synthesizer, or as the
system clock to a microprocessor controller.
POWER SUPPLY
VDD
Positive Power Supply (Pin 4)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.
VSS
Negative Power Supply (Pin 6)
The most negative supply potential. This pin is usually
ground.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145158-2 | 制造商:Motorola Inc 功能描述: |
| MC145158DW2 | 功能描述:IC SER-IN PLL FREQ SYNTH 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC145158DW2R2 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MC145159FN1R2 | 制造商:Motorola Inc 功能描述: |
| MC145159P1 | 制造商:Motorola Inc 功能描述: |
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