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參數(shù)資料
| 型號： | MC145151 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Parallel-Input PLL Frequency Synthesizer |
| 中文描述： | 并行輸入鎖相環(huán)頻率合成器 |
| 文件頁數(shù)： | 21/36頁 |
| 文件大?。?/td> | 718K |
| 代理商： | MC145151 |
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MC145151–2 through MC145158–2
MOTOROLA
21
14–BIT SHIFT REGISTER
7–BIT
÷
A
COUNTER
φ
V
φ
R
MC145158–2 BLOCK DIAGRAM
REFERENCE COUNTER LATCH
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT
LD
PDout
fin
OSCin
OSCout
ENB
14
10
7–BIT S/R
DATA
CLK
10
REFout
÷
A COUNTER
LATCH
14–BIT
÷
R COUNTER
14
MC
fR
fV
1–BIT
CONTROL
S/R
10–BIT S/R
÷
N COUNTER
LATCH
10–BIT
÷
N
COUNTER
CONTROL LOGIC
7
7
PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (Pin 8)
Input frequency from VCO output. A rising edge signal on
this input decrements the
÷
A and
÷
N counters. This input
has an inverter biased in the linear region to allow use with
ac coupled signals as low as 500 mV p–p. For larger ampli-
tude signals (standard CMOS logic levels), dc coupling may
be used.
CLK, DATA
Shift Clock, Serial Data Inputs (Pins 9, 10)
Each low–to–high transition of the CLK shifts one bit of
data into the on–chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic 1
selects the reference counter latch and a logic 0 selects the
÷
A,
÷
N counter latch. The data entry format is as follows:
L
M
C
FIRST DATA BIT INTO SHIFT REGISTER
÷
R
M
C
÷
N
FIRST DATA BIT INTO SHIFT REGISTER
÷
A
L
M
L
ENB
Latch Enable Input (Pin 11)
A logic high on this pin latches the data from the shift regis-
ter into the reference divider or
÷
N,
÷
A latches depending on
the control bit. The reference divider latches are activated if
the control bit is at a logic high and the
÷
N,
÷
A latches are
activated if the control bit is at a logic low. A logic low on this
pin allows the user to change the data in the shift registers
without affecting the counters. ENB is normally low and is
pulsed high to transfer data to the latches.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 1, 2)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSCin to ground and OSCout to ground.
OSCin may also serve as the input for an externally–gener-
ated reference signal. This signal is typically ac coupled to
OSCin, but for larger amplitude signals (standard CMOS log-
ic levels) dc coupling may also be used. In the external refer-
ence mode, no connection is required to OSCout.
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| MC145151-2 | Parallel-Input PLL Frequency Synthesizer |
| MC145152 | Inverting Dual High-Speed MOSFET Drivers with Internal Regulator 8-TSSOP |
| MC145155-2 | Parallel-Input PLL Frequency Synthesizer |
| MC145156 | Parallel-Input PLL Frequency Synthesizer |
| MC145155DW2 | Parallel-Input PLL Frequency Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145151DW2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145151DW2R2 | 功能描述:IC PAR-IN PLL FREQ SYNTH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MC145151P2 | 制造商:Motorola Inc 功能描述:Frequency Synthesizer, 28 Pin, Plastic, DIP |
| MC145152DW2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145152DW2R2 | 功能描述:IC PAR-IN PLL FREQ SYNTH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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