- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369899 > MC145151-2 (Motorola, Inc.) Parallel-Input PLL Frequency Synthesizer PDF資料下載
參數(shù)資料
| 型號： | MC145151-2 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Parallel-Input PLL Frequency Synthesizer |
| 中文描述： | 并行輸入鎖相環(huán)頻率合成器 |
| 文件頁數(shù)： | 6/36頁 |
| 文件大?。?/td> | 718K |
| 代理商： | MC145151-2 |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
MC145151–2 through MC145158–2
6
MOTOROLA
12 x 8 ROM REFERENCE DECODER
φ
V
φ
R
MC145152–2 BLOCK DIAGRAM
12–BIT
÷
R COUNTER
PHASE
DETECTOR
LOCK
DETECT
LD
fin
OSCin
OSCout
12
N0
N2
N4 N5
N7
N9
NOTE: N0 – N9, A0 – A5, and RA0 – RA2 have pull–up resistors that are not shown.
10–BIT
÷
N COUNTER
CONTROL
LOGIC
MC
6–BIT
÷
A COUNTER
A5
A3 A2
A0
RA2
RA1
RA0
PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (Pin 1)
Input to the positive edge triggered
÷
N and
÷
A counters.
fin is typically derived from a dual–modulus prescaler and is
ac coupled into the device. For larger amplitude signals
(standard CMOS logic levels) dc coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (Pins 4, 5, 6)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider. The
total reference divide values are as follows:
Reference Address Code
Total
Value
RA2
RA1
RA0
Divide
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
64
128
256
512
1024
1160
2048
N0 – N9
N Counter Programming Inputs (Pins 11 – 20)
The N inputs provide the data that is preset into the
÷
N
counter when it reaches the count of 0. N0 is the least signifi-
cant digit and N9 is the most significant. Pull–up resistors en-
sure that inputs left open remain at a logic 1 and require only
a SPST switch to alter data to the zero state.
A0 – A5
A Counter Programming Inputs
(Pins 23, 21, 22, 24, 25, 10)
The A inputs define the number of clock cycles of fin that
require a logic 0 on the MC output (see
Dual–Modulus
Prescaling
section). The A inputs all have internal pull–up
resistors that ensure that inputs left open will remain at a
logic 1.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSCin to ground and OSCout to ground.
OSCin may also serve as the input for an externally–gener-
ated reference signal. This signal is typically ac coupled to
OSCin, but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSCout.
OUTPUT PINS
φ
R,
φ
V
Phase Detector B Outputs (Pins 7, 8)
These phase detector outputs can be combined externally
for a loop–error signal.
If the frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by
φ
V pulsing low.
φ
R remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by
φ
R pulsing low.
φ
V remains essentially high.
If the frequency of fV = fR and both are in phase, then both
φ
V and
φ
R remain high except for a small minimum time
period when both pulse low in phase.
MC
Dual–Modulus Prescale Control Output (Pin 9)
Signal generated by the on–chip control logic circuitry for
controlling an external dual–modulus prescaler. The MC
level will be low at the beginning of a count cycle and will
remain low until the
÷
A counter has counted down from its
programmed value. At this time, MC goes high and remains
high until the
÷
N counter has counted the rest of the way
down from its programmed value (N – A additional counts
since both
÷
N and
÷
A are counting down during the first
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC145152 | Inverting Dual High-Speed MOSFET Drivers with Internal Regulator 8-TSSOP |
| MC145155-2 | Parallel-Input PLL Frequency Synthesizer |
| MC145156 | Parallel-Input PLL Frequency Synthesizer |
| MC145155DW2 | Parallel-Input PLL Frequency Synthesizer |
| MC145156P2 | Parallel-Input PLL Frequency Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145151DW2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145151DW2R2 | 功能描述:IC PAR-IN PLL FREQ SYNTH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC145151P2 | 制造商:Motorola Inc 功能描述:Frequency Synthesizer, 28 Pin, Plastic, DIP |
| MC145152DW2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145152DW2R2 | 功能描述:IC PAR-IN PLL FREQ SYNTH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。