參數(shù)資料
型號(hào): MC14514
廠商: Motorola, Inc.
英文描述: 4-Bit Transparent Latch/4-to-16 Line Decoder
中文描述: 4位透明Latch/4-to-16線譯碼器
文件頁(yè)數(shù): 3/8頁(yè)
文件大小: 254K
代理商: MC14514
MOTOROLA CMOS LOGIC DATA
387
MC14514B MC14515B
Characteristic
Symbol
VDD
Unit
Min
Typ #
Max
Output Rise Time
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
Output Fall Time
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
Propagation Delay Time; Data, Strobe to S
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.86 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
Inhibit Propagation Delay Times
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 117 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Setup Time
Data to Strobe
tTLH
5.0
10
15
180
90
65
360
180
130
ns
tTHL
5.0
10
15
100
50
40
200
100
80
ns
tPLH,
tPHL
5.0
10
15
550
225
150
1100
450
300
ns
tPLH,
tPHL
5.0
10
15
400
150
100
800
300
200
ns
tsu
5.0
10
15
250
100
75
125
50
38
ns
Hold Time
Strobe to Data
th
5.0
10
15
– 20
0
10
– 100
– 40
– 30
ns
Strobe Pulse Width
tWH
5.0
10
15
350
100
75
175
50
38
ns
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Drain Characteristics Test Circuit
EXTERNAL
POWER SUPPLY
VSS
STROBE
INHIBIT
D1
D2
D3
D4
VDD
VDS
ID
For MC14515B
1. For P–channel: Inhibit = VDD
2. For N–channel: Inhibit = VSS
2.
and D1–D4 constitute binary
2.
code for “output under test.”
For MC14514B
1. For P–channel: Inhibit = VSS
1.
and D1–D4 constitute
1.
binary code for “output
1.
under test.”
2. For N–channel: Inhibit = VDD
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
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