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參數(shù)資料
| 型號(hào)： | MC14514 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 4-Bit Transparent Latch/4-to-16 Line Decoder |
| 中文描述： | 4位透明Latch/4-to-16線譯碼器 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大?。?/td> | 254K |
| 代理商： | MC14514 |
MOTOROLA CMOS LOGIC DATA
MC14514B MC14515B
390
COMPLEX DATA ROUTING
Two MC14512 eight–channel data selectors are used here
with the MC14514B four–bit latch/decoder to effect a com-
plex data routing system. A total of 16 inputs from data regis-
ters are selected and transferred via a 3–state data bus to a
data distributor for rearrangement and entry into 16 output
registers. In this way sequential data can be re–routed or
intermixed according to patterns determined by data select
and distribution inputs.
Data is placed into the routing scheme via the eight inputs
on both MC14512 data selectors. One register is assigned to
each input. The signals on A0, A1, and A2 choose one of
eight inputs for transfer out to the 3–state data bus. A fourth
signal, labelled Dis, disables one of the MC14512 selectors,
assuring transfer of data from only one register.
In addition to a choice of input registers, 1 thru 16, the rate
of transfer of the sequential information can also be varied.
That is, if the MC14512 were addressed at a rate that is eight
times faster then the shift frequency of the input registers, the
most significant bit (MSB) from each register could be se-
lected for transfer to the data bus. Therefore, all of the most
significant bits from all of the registers can be transferred to
the data bus before the next most significant bit is presented
for transfer by the input registers.
Information from the 3–state bus is redistributed by the
MC14514B four–bit latch/decoder. Using the four–bit ad-
dress, D1 thru D4, the information on the inhibit line can be
transferred to the addressed output line to the desired output
registers, A thru P. This distribution of data bits to the output
registers can be made in many complex patterns. For exam-
ple, all of the most significant bits from the input registers can
be routed into output register A, all of the next most signifi-
cant bits into register B, etc. In this way horizontal, vertical, or
other methods of data slicing can be implemented.
DATA ROUTING SYSTEM
INPUT
REGISTERS
DATA
TRANSFER
DATA
DISTRIBUTION
OUTPUT
REGISTERS
3–STATE
DATA BUS
REGISTER A
REGISTER P
REGISTER 1
REGISTER 8
REGISTER 9
REGISTER 16
DATA
SELECT
STROBE
INHIBIT
DIS
DIS
Q
Q
D1 D2 D3 D4
A0 A1 A2
A0 A1 A2
D0
D1
D2
D3
D4
D5
D6
D7
M
M
M
D0
D1
D2
D3
D4
D5
D6
D7
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC14514BDWR2 | 4-Bit Transparent Latch/4-to-16 Line Decoder |
| MC14515BDWR2 | 4-Bit Transparent Latch/4-to-16 Line Decoder |
| MC14514B | 4-Bit Transparent Latch/4-to-16 Line Decoder |
| MC14514BCP | 4-Bit Transparent Latch/4-to-16 Line Decoder |
| MC14514BDW | Inverting Dual High-Speed MOSFET Drivers with Internal Regulator 8-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145145P1 | 制造商:Motorola Inc 功能描述: |
| MC145146L | 制造商:Motorola Inc 功能描述: |
| MC145149DWR2 | 制造商:Motorola Inc 功能描述: |
| MC14514BCP | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3-18V 4-Bit RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| MC14514BCPG | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3-18V 4-Bit Transparent RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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