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參數(shù)資料
| 型號： | MC145106 |
| 廠商： | Motorola, Inc. |
| 英文描述： | N+1 and OR-ing Power Rail Controller 14-TSSOP -40 to 85 |
| 中文描述： | 鎖相環(huán)頻率合成器 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 115K |
| 代理商： | MC145106 |
MC145106
MOTOROLA
4
TYPICAL CHARACTERISTICS*
* Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
OSCin, MAXIMUM FREQUENCY (MHz)
fin, MAXIMUM FREQUENCY (MHz)
50
40
30
20
10
0
0
5.0
10
15
20
25
+ 85
°
C
– 40
°
C
+ 25
°
C
50
40
30
20
10
0
0
5.0
10
15
20
25
+ 85
°
C
– 40
°
C
+ 25
°
C
V
D
V
D
Figure 1. Maximum Divider Input Frequency
versus Supply Voltage
Figure 2. Maximum Oscillator Input Frequency
versus Supply Voltage
TRUTH TABLE
Selection
P8
P7
P6
P5
P4
P3
P2
P1
P0
Divide by N
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
2*
3*
2
3
4
0
1
1
1
1
1
1
1
1
255
1
1
1
1
1
1
1
1
1
511
1: Voltage level = VDD.
0: Voltage level = 0 or open circuit input.
* The binary setting of 00000000 and 00000001 on P8 to P0 results
in a 2 and 3 division which is not in the 2N – 1 sequence. When pin
is not connected the logic signal on that pin can be treated as a “0”.
PIN DESCRIPTIONS
P0 – P8
Programmable Inputs (PDIP — Pins 17 – 9; SOG — Pins
19, 17 – 14, 12 – 9)
Programmable divider inputs (binary).
fin
Frequency Input (PDIP, SOG — Pin 2)
Frequency input to programmable divider (derived from
VCO).
OSCin, OSCout
Oscillator Input and Oscillator Output (PDIP, SOG —
Pins 3, 4)
Oscillator/amplifier input and output terminals.
LD
Lock Detector (PDIP, SOG — Pin 8)
LD is high when loop is locked, pulses low when out–of–
lock.
φ
Detout (PDIP, SOG — Pin 7)
Signal for control of external VCO, output high when fin/N is
less than the reference frequency; output low when fin/N is
greater than the reference frequency. Reference frequency is
the divided down oscillator — input frequency typically 5.0 or
10 kHz.
NOTE
Phase Detector Gain = VDD/4
π
.
FS
Reference Oscillator Frequency Division Select (PDIP,
SOG — Pin 6)
When using 10.24 MHz OSC frequency, this control selects
10 kHz, a “0” selects 5.0 kHz.
÷
2out (PDIP, SOG — Pin 5)
Reference OSC frequency divided by 2 output; when using
10.24 MHz OSC frequency, this output is 5.12 MHz for fre-
quency tripling applications.
VDD
Positive Power Supply (PDIP, SOG — Pin 1)
VSS
Ground (PDIP — Pin 18, SOG — Pin 20)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC145106DW | N+1 and OR-ing Power Rail Controller 14-TSSOP -40 to 85 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145106DW | 制造商:Motorola Inc 功能描述: |
| MC14510B | 制造商:Motorola Inc 功能描述: |
| MC14510BCP | 制造商:Panasonic Industrial Company 功能描述:IC |
| MC14510BF | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC14510BFEL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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