
MOTOROLA CMOS LOGIC DATA
MC14508B
344
The MC14508B dual 4–bit latch is constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic structure. The
part consists of two identical, independent 4–bit latches with separate Strobe
(ST) and Master Reset (MR) controls. Separate Disable inputs force the
outputs to a high impedance state and allow the devices to be used in time
sharing bus line applications.
These complementary MOS latches find primary use in buffer storage,
holding register, or general digital logic functions where low power
dissipation and/or high noise immunity is desired.
3–State Output
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable–of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
Parameter
VDD
DC Supply Voltage
Vin, Vout
Input or Output Voltage (DC or Transient)
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
Value
Unit
V
V
mA
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
±
10
PD
Tstg
TL
Power Dissipation, per Package
Storage Temperature
500
mW
C
– 65 to + 150
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
TRUTH TABLE
MR
ST
Disable
D3
D2
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
0
0
X
X
1
X
0
X
X
X
X
1
X
X
X = Don’t Care
CIRCUIT DIAGRAM
DIS
260
C
D1
0
0
1
0
0
X
X
X
D0
0
1
0
0
0
X
X
X
Q3
0
0
0
0
1
Q2
0
0
0
1
0
Latched
0
High Impedance
Q1
0
0
1
0
0
Q0
0
1
0
0
0
0
0
0
MR
ST
Dn
(TO OTHER THREE LATCHES)
VDD
Qn
VSS
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 623
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
BLOCK DIAGRAM
22
20
18
16
15
14
13
10
8
6
4
3
2
1
23
21
19
17
11
9
7
5
MR
ST
DIS
D0
D1
D2
D3
MR
ST
DIS
D0
D1
D2
D3
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
VDD = PIN 24
VSS = PIN 12