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參數(shù)資料
| 型號(hào)： | MC14506UBCL |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 2-Wide, 2-Input Expandable AND-OR-INVERT Gate |
| 中文描述： | 4000/14000/40000 SERIES, DUAL 4-INPUT AND-OR-INVERT GATE, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大?。?/td> | 238K |
| 代理商： | MC14506UBCL |
MOTOROLA CMOS LOGIC DATA
3
MC14506UB
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Data Propagation Delay Time
tPLH = (1.7 ns/pF) CL + 210 ns
tPLH = (0.66 ns/pF) CL + 77 ns
tPLH = (0.5 ns/pF) CL + 50 ns
tPHL = (1.7 ns/pF) CL + 185 ns
tPHL = (0.66 ns/pF) CL + 62 ns
tPHL = (0.5 ns/pF) CL + 40 ns
Expand Propagation Delay Time
tPLH = (1.7 ns/pF) CL + 95 ns
tPLH = (0.66 ns/pF) CL + 42 ns
tPLH = (0.5 ns/pF) CL + 25 ns
tPHL = (1.7 ns/pF) CL + 115 ns
tPHL = (0.66 ns/pF) CL + 47 ns
tPHL = (0.5 ns/pF) CL + 30 ns
Inhibit Propagation Delay Time
tPLH = (1.7 ns/pF) CL + 135 ns
tPLH = (0.66 ns/pF) CL + 67 ns
tPLH = (0.5 ns/pF) CL + 40 ns
tPHL = (1.7 ns/pF) CL + 145 ns
tPHL = (0.66 ns/pF) CL + 62 ns
tPHL = (0.5 ns/pF) CL + 35 ns
3–State Propagation Delay Time
“1” to High Impedance
tTLH, tTHL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
tPLH
5.0
10
15
—
—
—
295
110
75
580
225
180
ns
tPHL
5.0
10
15
—
—
—
270
95
65
480
175
140
ns
tPLH
5.0
10
15
—
—
—
180
75
50
430
160
125
ns
tPHL
5.0
10
15
—
—
—
200
80
55
330
110
90
ns
tPLH
5.0
10
15
—
—
—
220
100
65
500
225
160
ns
tPHL
5.0
10
15
—
—
—
230
95
60
400
175
150
ns
tPHZ
5.0
10
15
—
—
—
60
45
35
150
110
90
ns
“0” to High Impedance
tPLZ
5.0
10
15
—
—
—
90
55
40
225
140
100
ns
High Impedance to “1”
tPZH
5.0
10
15
—
—
—
110
50
40
300
125
100
ns
High Impedance to “0”
tPZL
5.0
10
15
—
—
—
170
70
50
425
175
125
ns
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” Is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Typical Voltage Transfer Characteristics
(a) Expand Inputs
(b) Data Inputs
16
14
12
10
8.0
6.0
4.0
2.0
0
16
14
12
10
8.0
6.0
4.0
2.0
0
Vin, INPUT VOLTAGE (Vdc)
V
abc
c
a
b
a
b
c
VDD = 15 Vdc
10 Vdc
5.0 Vdc
a
b
c
TA = + 125
°
C
TA = + 25
°
C
TA = – 55
°
C
UNUSED INPUTS
CONNECTED TO
VSS
16
14
12
10
8.0
6.0
4.0
2.0
0
16
14
12
10
8.0
6.0
4.0
2.0
0
Vin, INPUT VOLTAGE (Vdc)
V
a
b
c
TA = + 125
°
C
TA = + 25
°
C
TA = – 55
°
C
A AND B CONNECTED TO Vin
ENABLE INPUT CONNECTED TO
VDD. OTHER INPUTS CONNECTED
TO VSS.
VDD = 15 Vdc
10 Vdc
5.0 Vdc
a
b
c
a
b
a
c
b
c
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