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參數(shù)資料
| 型號： | MC145053D |
| 廠商： | MOTOROLA INC |
| 元件分類： | ADC |
| 英文描述： | -48V Hot Swap Controller 8-MSOP -40 to 85 |
| 中文描述： | 5-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO14 |
| 封裝： | SOG-14 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大小： | 166K |
| 代理商： | MC145053D |
MC145053
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
11
APPLICATIONS INFORMATION
DESCRIPTION
This example application of the MC145053 ADC interfaces
four analog signals to a microprocessor.
Figure 15 illustrates how the MC145053 is used as a cost-
effective means to simplify this type of circuit design. Utilizing
one ADC, four analog inputs are interfaced to a CMOS or
NMOS microprocessor with a serial peripheral interface
(SPI) port. Processors with National Semiconductor’s
MICROWIRE serial port may also be used. Full duplex
operation optimizes throughput for this system.
DIGITAL DESIGN CONSIDERATIONS
Motorola’s MC68HC05C4 CMOS MCU may be chosen to
reduce power supply size and cost. The NMOS MCUs may
be used if power consumption is not critical. A VDD or VSS
0.1
μ
F bypass capacitor should be closely mounted to the
ADC.
The MC145053 has the end-of-conversion (EOC) signal at
output pin 1 to define when data is ready.
ANALOG DESIGN CONSIDERATIONS
Analog signal sources with output impedances of less than
1 k
may be directly interfaced to the ADC, eliminating the
need for buffer amplifiers. Separate lines connect the Vref
and VAG pins on the ADC with the controllers to provide
isolation from system noise.
Although not indicated in Figure 15, the Vref and sensor
output lines may need to be shielded, depending on their
length and electrical environment. This should be verified
during prototyping with an oscilloscope. If shielding is
required, a twisted pair or foil-shielded wire (not coax) is
appropriate for this low frequency application. One wire of
the pair or the shield must be VAG.
A reference circuit voltage of 5 volts is used for the applica-
tion shown in Figure 15. However, the reference circuitry
may be simplified by tying VAG to system ground and Vref to
the system’s positive supply. (See Figure 16.)
A bypass capacitor of approximately 0.22
μ
F across the
Vref and VAG pins is recommended. These pins are adjacent
on the ADC package which facilitates mounting the capacitor
very close to the ADC.
SOFTWARE CONSIDERATIONS
The software flow for acquisition is straightforward. The
four analog inputs, AN0 through AN3, are scanned by read-
ing the analog value of the previously addressed channel
into the MCU and sending the address of the next channel to
be read to the ADC, simultaneously.
The designer utilizing the MC145053 has the end-of-con-
version signal (at pin 1) to define the conversion interval.
EOC may be used to generate an interrupt, which is serviced
by reading the serial data from the ADC. The software flow
should then process and format the data.
When this ADC is used with a 16-bit (2-byte) transfer, there
are two types of offsets involved. In the first type of offset, the
channel information sent to the ADCs is offset by 12 bits.
That is, in the 16-bit stream, only the first 4 bits (4 MSBs)
contain the channel information. The balance of the bits are
don’t cares. This results in 3 don’t-care nibbles, as shown in
Table 2. The second type of offset is in the conversion result
returned from the ADC; this is offset by 6 bits. In the 16-bit
stream, the first 10 bits (10 MSBs) contain the conversion
result. The last 6 bits are zeroes. The hexadecimal result is
shown in the first column of Table 3. The second column
shows the result after the offset is removed by a micro-
processor routine. If the 16-bit format is used, the ADC can
transfer one continuous 16-bit stream or two intermittent 8-bit
streams.
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