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參數(shù)資料
| 型號： | MC145051P |
| 廠商： | MOTOROLA INC |
| 元件分類： | ADC |
| 英文描述： | 10-Bit A/D Converter with Serial Interface |
| 中文描述： | 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 181K |
| 代理商： | MC145051P |
MC145050 MC145051
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
7
four rising edges of SCLK, and the previous 10-bit conver-
sion result is shifted out on the first nine falling edges of
SCLK. After the fourth rising edge of SCLK, the new mux ad-
dress is available; therefore, on the next edge of SCLK (the
fourth falling edge), the analog input voltage on the selected
mux input begins charging the RC DAC and continues to do
so until the tenth falling edge of SCLK. After this tenth SCLK
edge, the analog input voltage is disabled from the RC DAC
and the RC DAC begins the “hold” portion of the A/D conver-
sion sequence. Also upon this tenth SCLK edge, control of
the internal circuitry is transferred to ADCLK which drives the
successive approximation logic to complete the conversion.
If 16 SCLK cycles are used during each transfer, then there
is a constraint on the minimum SCLK frequency. Specifically,
there must be at least one rising edge on SCLK before the
A/D conversion is complete. If the SCLK frequency is too low
and a rising edge does not occur during the conversion, the
chip is thrown out of sync with the processor and CS needs
to be toggled in order to restore proper operation. If 10
SCLKs are used per transfer, then there is no lower frequen-
cy limit on SCLK. Also note that if the ADC is operated such
that CS is inactive high between transfers, then the number
of SCLK cycles per transfer can be anything between 10 and
16 cycles, but the “rising edge” constraint is still in effect if
more than 10 SCLKs are used. (If CS stays active low for
multiple transfers, the number of SCLK cycles must be either
10 or 16.)
ADCLK
A/D Conversion Clock Input (Pin 19, MC145050 Only)
This pin clocks the dynamic A/D conversion sequence,
and may be asynchronous to SCLK. Control of the chip
passes to ADCLK after the tenth falling edge of SCLK. Con-
trol of the chip is passed back to SCLK after the successive
approximation conversion sequence is complete (44 ADCLK
cycles), or after a valid chip select is recognized. ADCLK
also drives the CS recognition logic. The chip ignores transi-
tions on CS unless the state remains for a setup time plus
two falling edges of ADCLK. The source driving ADCLK must
be free running.
EOC
End-of-Conversion Output (Pin 19, MC145051 Only)
EOC goes low on the tenth falling edge of SCLK. A low-to-
high transition on EOC occurs when the A/D conversion is
complete and the data is ready for transfer.
ANALOG INPUTS AND TEST MODE
AN0 through AN10
Analog Multiplexer Inputs (Pins 1 – 9, 11, 12)
The input AN0 is addressed by loading $0 into the mux ad-
dress register. AN1 is addressed by $1, AN2 by $2,
…
, AN10
by $A. Table 2 shows the input format for a 16-bit stream.
The mux features a break-before-make switching structure
to minimize noise injection into the analog inputs. The source
resistance driving these inputs must be
During normal operation, leakage currents through the
analog mux from unselected channels to a selected channel
and leakage currents through the ESD protection diodes on
the selected channel occur. These leakage currents cause
an offset voltage to appear across any series source resis-
tance on the selected channel. Therefore, any source resis-
tance greater than 1 k
(Motorola test condition) may induce
errors in excess of guaranteed specifications.
There are three tests available that verify the functionality
of all the control logic as well as the successive approxima-
tion comparator. These tests are performed by addressing
$B, $C, or $D and they convert a voltage of (Vref + VAG)/2,
VAG, or Vref, respectively. The voltages are obtained internal-
ly by sampling Vref or VAG onto the appropriate elements of
the RC DAC during the sample phase. Addressing $B, $C, or
$D produces an output of $200 (half scale), $000, or $3FF
(full scale), respectively, if the converter is functioning prop-
erly. However, deviation from these values occurs in the
presence of sufficient system noise (external to the chip) on
VDD, VSS, Vref, or VAG.
1 k
.
POWER AND REFERENCE PINS
VSS and VDD
Device Supply Pins (Pins 10 and 20)
VSS is normally connected to digital ground; VDD is con-
nected to a positive digital supply voltage. Low frequency
(VDD – VSS) variations over the range of 4.5 to 5.5 volts do
not affect the A/D accuracy. (See the Operations Ranges
Table for restrictions on Vref and VAG relative to VDD and
VSS.) Excessive inductance in the VDD or VSS lines, as on
automatic test equipment, may cause A/D offsets >
±
1 LSB.
Use of a 0.1
μ
F bypass capacitor across these pins is recom-
mended.
VAG and Vref
Analog Reference Voltage Pins (Pins 13 and 14)
Analog reference voltage pins which determine the lower
and upper boundary of the A/D conversion. Analog input volt-
ages
≥
Vref produce a full scale output and input voltages
≤
VAG produce an output of zero. CAUTION: The analog
input voltage must be
≥
VSS and
≤
VDD. The A/D conversion
result is ratiometric to Vref – VAG. Vref and VAG must be as
noise-free as possible to avoid degradation of the A/D con-
version. Ideally, Vref and VAG should be single-point con-
nected to the voltage supply driving the system’s
transducers. Use of a 0.22
μ
F bypass capacitor across these
pins is strongly urged.
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