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參數(shù)資料
| 型號： | MC145050 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 10-Bit A/D Converter with Serial Interface |
| 中文描述： | 10位A / D轉換器的串行接口 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 181K |
| 代理商： | MC145050 |
MC145050 MC145051
4
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
Figure
Symbol
Parameter
Guaranteed
Limit
Unit
1
f
Clock Frequency, SCLK
(10-bit xfer) Min
(11- to 16-bit xfer) Min
(10- to 16-bit xfer) Max)
Note: Refer to twH, twL below
0
Note 1
2.1
MHz
1
f
Clock Frequency, ADCLK
Note: Refer to twH, twL below
Minimum
Maximum
500
2.1
kHz
MHz
1
twH
Minimum Clock High Time
ADCLK
SCLK
190
190
ns
1
twL
Minimum Clock Low Time
ADCLK
SCLK
190
190
ns
1, 7
tPLH, tPHL
th
tPLZ, tPHZ
tPZL, tPZH
Maximum Propagation Delay, SCLK to Dout
Minimum Hold Time, SCLK to Dout
Maximum Propagation Delay, CS to Dout High-Z
Maximum Propagation Delay, CS to Dout Driven
125
ns
1, 7
10
ns
2, 7
150
ns
2, 7
MC145050
MC145051
2 ADCLK cycles + 300
2.3
ns
μ
s
3
tsu
th
td
tsu
Minimum Setup Time, Din to SCLK
Minimum Hold Time, SCLK to Din
Maximum Delay Time, EOC to Dout (MSB)
Minimum Setup Time, CS to SCLK
100
ns
3
0
ns
4, 7, 8
MC145051
100
ns
5
MC145050
MC145051
2 ADCLK cycles + 425
2.425
ns
μ
s
—
tCSd
Minimum Time Required Between 10th SCLK Falling
Edge (
≤
0.8 V) and CS to Allow a Conversion
MC145050
MC145051
44
Note 2
ADCLK
cycles
—
tCAs
Maximum Delay Between 10th SCLK Falling Edge
(
≤
2 V) and CS to Abort a Conversion
MC145050
MC145051
36
9
ADCLK
cycles
μ
s
5
th
Minimum Hold Time, Last SCLK to CS
0
ns
6, 8
tPHL
tr, tf
Maximum Propagation Delay, 10th SCLK to EOC
MC145051
2.35
μ
s
1
Maximum Input Rise and Fall Times
SCLK
ADCLK
Din, CS
1
250
10
ms
ns
μ
s
1, 4, 6 – 8
tTLH, tTHL
Cin
Maximum Output Transition Time, Any Output
300
ns
—
Maximum Input Capacitance
AN0 – AN10
ADCLK, SCLK, CS, Din
55
15
pF
—
Cout
Maximum Three-State Output Capacitance
Dout
15
pF
NOTES:
1. After the 10th SCLK falling edge (
≤
2 V), at least 1 SCLK rising edge (
≥
2 V) must occur within 38 ADCLKs (MC145050) or 18.5
μ
s
(MC145051).
2. On the MC145051, a CS edge may be received immediately after an active transition on the EOC pin.
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