參數(shù)資料
型號(hào): MC145012DW
廠商: Freescale Semiconductor
文件頁數(shù): 3/14頁
文件大?。?/td> 0K
描述: IC SMOKE DETECT WITH I/O 16SOIC
標(biāo)準(zhǔn)包裝: 47
類型: 煙霧探測(cè)器
輸入類型: 光電
輸出類型: 電壓
電流 - 電源: 8µA
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 管件
Sensors
Freescale Semiconductor
11
MC145012
CALIBRATION
To facilitate checking the sensitivity and calibrating smoke
detectors, the MC145012 can be placed in a calibration
mode. In this mode, certain device pins are controlled/
reconfigured as shown in Table 5. To place the part in the
calibration mode, Pin 16 (Test) must be pulled below the VSS
pin with 100
A continuously drawn out of the pin for at least
one cycle on the OSC pin. To exit this mode, the Test pin is
floated for at least one OSC cycle.
In the calibration mode, the IRED pulse rate is increased
to one for every OSC cycle. Also, Strobe is always active low.
Figure 9. Recommended PCB Layout
Table 5. Configuration of Pins in the Calibration Mode
Description
Pin
Comment
I/O
7
Disabled as an output. Forcing this pin high places the photo amp output on Pin 1 or 2, as determined by Low-
Supply Trip. The amp's output appears as pulses and is referenced to VDD etc.
Low-Supply Trip
15
If the I/O pin is high, Pin 15 controls which gain capacitor is used. Low: normal gain, amp output on Pin 1. High:
supervisory gain, amp output on Pin 2.
Feedback
10
Driving this input high enables hysteresis (10% gain increase) in the photo amp; Pin 15 must be low.
OSC
12
Driving this input high brings the internal clock high. Driving the input low brings the internal clock low. If
desired, the RC network for the oscillator may be left intact; this allows the oscillator to run similar to the normal
mode of operation.
Silver
9
This pin becomes the smoke comparator output. When the OSC pin is toggling, positive pulses indicate that
smoke has been detected. A static low level indicates no smoke.
Brass
8
This pin becomes the smoke integrator output. That is, 2 consecutive smoke detections are required for “on”
(static high level) and 2 consecutive no-detections for “off” (static low level).
NOTES: Illustration is bottom view of layout using a DIP. Top view for SOIC layout is mirror image.
Optional potentiometer R9 is not included.
Drawing is not to scale.
Leads on D2, R11, R8, and R10 and their associated traces must be kept as short as possible. This practice minimizes noise
pick up.
Pin 3 must be decoupled from all other traces.
Do Not Run Any
Additional Traces
In This Region
PIN 8
Pin 16
Pin 9
Pin 1
R8
R11
D2
C2
R14
C1
R10
0
MOUNTED IN
CHAMBER
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