參數資料
| 型號： | MC14094BFG |
| 廠商： | ON Semiconductor |
| 文件頁數： | 1/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SHIFT REGISTER 8STG 16SOEIAJ |
| 產品變化通告： | Product Discontinuation 30/Sept/2011 |
| 標準包裝： | 50 |
| 系列： | 4000B |
| 邏輯類型： | 移位寄存器 |
| 輸出類型： | 三態(tài) |
| 元件數： | 1 |
| 每個元件的位元數： | 8 |
| 功能： | 串行至并行 |
| 電源電壓： | 3 V ~ 18 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 16-SOEIAJ |
| 包裝： | 管件 |
Semiconductor Components Industries, LLC, 2013
May, 2013 Rev. 9
1
Publication Order Number:
MC14094B/D
MC14094B
8-Stage Shift/Store Register
with Three-State Outputs
The MC14094B combines an 8stage shift register with a data latch
for each stage and a 3state output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The QS output data is for use in
highspeed cascaded systems. The QS output data is shifted on the
following negative clock transition for use in lowspeed cascaded systems.
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while
strobe is high.
Outputs of the eight data latches are controlled by 3state buffers which
are placed in the highimpedance state by a logic Low on Output Enable.
Features
3State Outputs
Capable of Driving Two LowPower TTL Loads or One LowPower
Schottky TTL Load Over the Rated Temperature Range
Input Diode Protection
Data Latch
Dual Outputs for Data Out on Both Positive and
Negative Clock Transitions
Useful for SerialtoParallel Data Conversion
PinforPin Compatible with CD4094B
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package (Note 1)
500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout
should be constrained to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING DIAGRAMS
PDIP16
P SUFFIX
CASE 648
MC14094BCP
AWLYYWWG
SOIC16
D SUFFIX
CASE 751B
TSSOP16
DT SUFFIX
CASE 948F
14094BG
AWLYWW
14
094B
ALYWG
G
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= PbFree Indicator
SOEIAJ16
F SUFFIX
CASE 966
MC14094B
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
16
1
16
1
16
1
16
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