參數(shù)資料
型號: MC14093BDTEL
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: IEEE 802.3af PoE Powered Device Controllers 8-SOIC -40 to 85
中文描述: 4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝: PLASTIC, TSSOP-14
文件頁數(shù): 1/8頁
文件大小: 215K
代理商: MC14093BDTEL
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14093B/D
!
The MC14093B Schmitt trigger is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B
may be used in place of the MC14011B quad 2–input NAND gate for
enhanced noise immunity or to “square up” slowly changing
waveforms.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Triple Diode Protection on All Inputs
Pin–for–Pin Compatible with CD4093
Can be Used to Replace MC14011B
Independent Schmitt–Trigger at each Input
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±
10
mA
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
T
A
Ambient Temperature Range
–55 to +125
°
C
T
stg
Storage Temperature Range
–65 to +150
°
C
T
L
Lead Temperature
(8–Second Soldering)
260
°
C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
A
WL or L
YY or Y
WW or W = Work Week
= Assembly Location
= Wafer Lot
= Year
Device
Package
Shipping
ORDERING INFORMATION
MC14093BCP
PDIP–14
2000/Box
MC14093BD
SOIC–14
2750/Box
MC14093BDR2
SOIC–14
2500/Tape & Reel
MC14093BDT
TSSOP–14
MC14093BF
SOEIAJ–14
96/Rail
See Note 1.
MARKING
DIAGRAMS
14
1
PDIP–14
P SUFFIX
CASE 646
MC14093BCP
AWLYYWW
SOIC–14
D SUFFIX
CASE 751A
TSSOP–14
DT SUFFIX
CASE 948G
1
14
14093B
AWLYWW
14
093B
ALYW
1
14
SOEIAJ–14
F SUFFIX
CASE 965
1
14
MC14093B
AWLYWW
MC14093BFEL
SOEIAJ–14
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MC14093BDTR2
TSSOP–14
2500/Tape & Reel
MC14093BDTEL
TSSOP–14
2000/Tape & Reel
相關PDF資料
PDF描述
MC14093BDTR2 IEEE 802.3af PoE Powered Device Controllers 8-SOIC -40 to 85
MC14093BF IEEE 802.3af PoE Powered Device Controllers 8-SOIC -40 to 85
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MC14094B 8 Stage Shift/Store Register with Three State Outputs(8位移位寄存器(三態(tài)輸出))
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