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參數(shù)資料
| 型號(hào)： | MC14070BFL2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類(lèi)： | 門(mén)電路 |
| 英文描述： | 4000/14000/40000 SERIES, QUAD 2-INPUT XOR GATE, PDSO14 |
| 封裝： | EIAJ, PLASTIC, SOIC-14 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 116K |
| 代理商： | MC14070BFL2 |
Semiconductor Components Industries, LLC, 2000
August, 2000 – Rev. 4
1
Publication Order Number:
MC14070B/D
MC14070B, MC14077B
CMOS SSI
Quad Exclusive “OR” and “NOR” Gates
The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic
structure. These complementary MOS logic gates find primary use
where low power dissipation and/or high noise immunity is desired.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
MC14070B — Replacement for CD4030B and CD4070B Types
MC14077B — Replacement for CD4077B Type
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
–0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
–0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
–55 to +125
°C
Tstg
Storage Temperature Range
–65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
xx
= Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC140XXBCP
PDIP–14
2000/Box
MC140XXBD
SOIC–14
2750/Box
MC140XXBDR2
SOIC–14
2500/Tape & Reel
MC140XXBF
SOEIAJ–14
See Note 1.
MARKING
DIAGRAMS
1
14
PDIP–14
P SUFFIX
CASE 646
MC140xxBCP
AWLYYWW
SOIC–14
D SUFFIX
CASE 751A
1
14
140xxB
AWLYWW
SOEIAJ–14
F SUFFIX
CASE 965
1
14
MC140xxB
ALYW
MC140XXBFEL
SOEIAJ–14
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
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| MC14070BF | 4000/14000/40000 SERIES, QUAD 2-INPUT XOR GATE, PDSO14 |
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| MC14081BD | 4000/14000/40000 SERIES, QUAD 2-INPUT AND GATE, PDSO14 |
| MC14001BCP | 4000/14000/40000 SERIES, QUAD 2-INPUT NOR GATE, PDIP14 |
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