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| 型號(hào)： | MC14060BCP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 14-Bit Binary Counter and Oscillator |
| 中文描述： | 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 237K |
| 代理商： | MC14060BCP |
MOTOROLA CMOS LOGIC DATA
MC14060B
2
per Pin
PD
Tstg
TL
* Maximum Ratings are those values beyond which damage to the device may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Power Dissipation, per Package
Storage Temperature
500
– 65 to + 150
mW
C
Lead Temperature (8–Second Soldering)
260
C
ELECTRICAL CHARACTERISTICS
– 55 C
Min
Characteristic
Symbol
25 C
Min
Typ #
Max
125 C
Max
Min
Unit
Output Voltage
“0” Level
5.0
15
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
Max
0.05
0.05
V
VOL
“1” Level
5.0
4.95
—
4.95
5.0
—
4.95
—
V
(VO = 4.5 or 0.5 V)
5.0
10
—
7.0
1.5
—
—
7.0
2.25
5.50
1.5
—
—
7.0
1.5
—
(VO = 1.0 or 9.0 V)
Input Voltage
(VO = 9.0 Vdc)
“0” Level
and Output 10)
Vdc
(VO = 1.5 Vdc)
VIL
VIH
10
5.0
15
—
4.0
12.5
2.0
—
—
—
4.0
12.5
4.50
2.75
8.25
2.0
—
—
—
4.0
12.5
2.0
—
—
Vdc
Output Drive Current
(VOH = 2.5 V)
(VOH = 9.5 V)
5.0
10
– 3.0
– 1.6
—
—
– 2.4
– 1.3
– 4.2
– 2.25
—
—
– 1.7
– 0.9
—
—
mA
Input Current
(Except Source
Sink
IOL
5.0
15
0.64
4.2
—
—
0.51
3.4
0.88
8.8
—
—
0.36
2.4
—
—
mA
(VOL = 0.4 V)
Cin
IDD
15
—
±
0.1
—
±
0.00001
±
0.1
—
±
1.0
μ
A
Input Capacitance (Vin = 0)
Quiescent Current
—
5.0
—
—
—
5.0
—
—
5.0
0.005
7.5
5.0
—
—
—
150
pF
μ
A
(Dynamic plus Quiescent,
all buffers switching)
10
IT = (0.54
μ
A/kHz) f + IDD
# Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
VDD.
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