參數(shù)資料
型號: MC14049UBDTELG
廠商: ON Semiconductor
文件頁數(shù): 1/8頁
文件大?。?/td> 0K
描述: IC INVERTER HEX 1-INPUT 16TSSOP
標(biāo)準(zhǔn)包裝: 96
系列: 4000B
邏輯類型: 反相器
電路數(shù): 6
輸入數(shù): 1
電源電壓: 3 V ~ 18 V
電流 - 靜態(tài)(最大值): 4µA
輸出電流高,低: 10mA,40mA
邏輯電平 - 低: 1 V ~ 2.5 V
邏輯電平 - 高: 4 V ~ 12.5 V
額定電壓和最大 CL 時的最大傳播延遲: 50ns @ 15V,50pF
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 16-TSSOP
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
包裝: 管件
Semiconductor Components Industries, LLC, 2013
May, 2013 Rev. 8
1
Publication Order Number:
MC14049UB/D
MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logiclevel conversion using only one
supply voltage, VDD. The inputsignal high level (VIH) can exceed the
VDD supply voltage for logiclevel conversions. Two TTL/DTL
Loads can be driven when the device is used as CMOStoTTL/DTL
converters (VDD = 5.0 V, VOL v 0.4 V, IOL ≥ 3.2 mA). Note that pins
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation.
Features
High Source and Sink Currents
HightoLow Level Converter
Supply Voltage Range = 3.0 V to 18 V
Meets JEDEC UB Specifications
VIN can exceed VDD
Improved ESD Protection on All Inputs
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin
Input Voltage Range
(DC or Transient)
0.5 to +18.0
V
Vout
Output Voltage Range
(DC or Transient)
0.5 to VDD
+0.5
V
Iin
Input Current
(DC or Transient) per Pin
±10
mA
Iout
Output Current
(DC or Transient) per Pin
+45
mA
PD
Power Dissipation, per Package (Note 1)
Plastic
SOIC
825
740
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature (8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: All Packages: See Figure 4.
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the VSS pin, only. Extra precautions
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this highimpedance circuit. For proper operation, the ranges
VSS v Vin v 18 V and VSS v Vout v VDD are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
MARKING
DIAGRAMS
PDIP16
P SUFFIX
CASE 648
MC14049UBCP
AWLYYWWG
SOIC16
D SUFFIX
CASE 751B
TSSOP16
DT SUFFIX
CASE 948F
14049UBG
AWLYWW
SOEIAJ16
F SUFFIX
CASE 966
MC14049UB
ALYWG
16
1
16
1
16
14
049UB
ALYW G
G
1
16
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= PbFree Package
(Note: Microdot may be in either location)
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