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參數(shù)資料
| 型號： | MC14035B |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4-Bit Parallel-In/Parallel-Out Shift Register |
| 中文描述： | 4位Parallel-In/Parallel-Out移位寄存器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 224K |
| 代理商： | MC14035B |
MOTOROLA CMOS LOGIC DATA
MC14035B
146
Characteristic
Output Rise and Fall Time
TTLH, TTHL = (0.75 ns/pF) CL + 12.5 ns
TTLH, TTHL = (0.55 ns/pF) CL + 12.5 ns
TPLH, TPHL = (0.70 ns/pF) CL + 89 ns
Symbol
tTLH,
Vdc
10
15
Min
—
—
Typ #
50
40
Max
100
80
Unit
ns
10
10
10
15
—
165
175
25
130
45
40
10
260
—
—
—
15
5.0
15
5.0
5.0
5.0
10
10
10
10
15
Clock Pulse Frequency
fcl
—
—
10
500
40
500
200
20
200
40
40
5
MHz
J–K to Clock Setup Time
tsu
2.5
6.0
120
1.2
2.0
3.0
—
—
—
—
—
—
—
—
ns
Clock to J–K Hold Time
th
– 40
ns
P/S to Clock Setup Time
25
10
ns
– 20
20
0
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Timing Diagram
RESET
50%
trem
CLOCK
INPUT
J–K
INPUT
P/S
INPUT
DP0
INPUT
Q0
T/C INPUT LOW
50%
50%
tsu
50%
tWH
1/fcl
th
tsu
tsu
th
tTHL
tTLH
th
tsu
90%
10%
50%
tPHL
tPLH
tPHL
tPLH
50%
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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