MOTOROLA CMOS LOGIC DATA
137
MC14034B
Characteristic
Output Rise Time A or B
tTLH = (1.1 ns/pF) CL + 10 ns
Output Fall Time A or B
tTHL = (0.55 ns/pF) CL + 9.5 ns
Propagation Delay Time
B (A) Parallel Data Output
tPLH, tPHL = (1.7 ns/pF) CL + 440 ns
Propagation Delay Time
tPLH, tPHL = (1.7 ns/pF) CL + 420 ns
Symbol
Vdc
15
Min
—
Typ #
65
Max
130
Unit
ns
tTHL
15
—
40
80
ns
tPLH,
ns
tPLH,
5.0
15
—
—
525
145
1050
290
ns
5.0
10
—
140
505
70
1010
—
10
15
—
—
6.0
8.0
3.0
4.0
Clock Pulse Rise
tTLH, tTHL
5.0
15
—
—
—
—
15
4
s
A, B Input Setup Time
tsu
5.0
100
35
—
ns
10
270
90
—
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
TRUTH TABLE
“A” Enable
P/S
A/B
A/S
Mode
Operation
0
0
0
X
Serial
Synchronous Serial data input, A and B Parallel data outputs disabled.
0
0
1
X
Serial
Synchronous Serial data input, B–Parallel data output.
0
1
0
0
Parallel
B Synchronous Parallel data inputs, A–Parallel data outputs disabled.
0
1
0
1
Parallel
B Asynchronous Parallel data inputs, A–Parallel data outputs disabled.
0
1
1
0
Parallel
A–Parallel data inputs disabled, B–Parallel data outputs.
0
1
1
1
Parallel
A–Parallel data inputs disabled, B–Parallel data outputs.
1
0
0
X
Serial
Synchronous serial data input, A–Parallel data output.
1
0
1
X
Serial
Synchronous serial data input, B–Parallel data output.
1
1
0
0
Parallel
B–Synchronous Parallel data input, A–Parallel data output.
1
1
0
1
Parallel
B–Asynchronous Parallel data input, A–Parallel data output.
1
1
1
0
Parallel
A–Synchronous Parallel data input, B–Parallel data output.
1
1
1
1
Parallel
A–Asynchronous Parallel data input, B–Parallel data output.
X = Don’t Care
Outputs change at positive transition of clock in the serial mode and when the A/S input is low in the parallel mode. During transfer from parallel
to serial operation, A/S should remain low in order to prevent DS transfer into flip–flops.