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參數(shù)資料
| 型號： | MC14027BFEL |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual J-K Flip-Flop |
| 中文描述： | 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | EIAJ, PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 213K |
| 代理商： | MC14027BFEL |
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
107
MC14027B
"
The MC14027B dual J–K flip–flop has independent J, K, Clock (C), Set (S)
and Reset (R) inputs for each flip–flop. These devices may be used in
control, register, or toggle functions.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Swing Independent of Fanout
Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going edge
of the clock pulse
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
(Voltages Referenced to VSS)
per Pin
Tstg
TL
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
Power Dissipation, per Package
Storage Temperature
500
– 65 to + 150
mW
C
Lead Temperature (8–Second Soldering)
260
C
TRUTH TABLE
Inputs
Outputs*
C
J
K
S
R
Qn
0
Qn+1
1
Qn+1
0
1
X
0
0
X
0
0
0
1
1
0
0
X
0
0
0
0
1
X
1
0
0
1
0
1
1
1
0
0
Qo
Qo
Qo
X
X
0
0
X
Qn
1
Qn
0
X
X
X
1
0
X
X
X
X
0
1
X
0
1
X
X
X
1
1
X
1
1
X = Don’t Care
= Level Change
= Present State
* = Next State
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS
≤
(Vin or Vout)
≤
VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
No
Change
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
!
!
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
BLOCK DIAGRAM
12
11
13
10
9
4
5
3
6
7
14
15
2
1
S
S
R
R
K
C
J
K
C
J
Q
Q
Q
Q
VDD = PIN 16
VSS = PIN 8
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| MC14027BDR2 | Dual-Slot Cardbus Power-Interface Switches for Serial PCMCIA Controllers 30-SSOP -40 to 85 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC14027BFELG | 功能描述:觸發(fā)器 3-18V CMOS Dual JK-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC14027BFL1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC14027BFR1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC14027BL2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC14028B | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:BCD−To−Decimal Decoder Binary−To−Octal Decoder |
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