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參數(shù)資料
| 型號(hào)： | MC14024B |
| 廠商： | Motorola, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 7-Stage Ripple Counter |
| 中文描述： | 7級(jí)紋波計(jì)數(shù)器 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大小： | 210K |
| 代理商： | MC14024B |
MOTOROLA CMOS LOGIC DATA
101
MC14024B
VDD
10
—
0.05
—
0
0.05
—
0.05
Vin = 0 or VDD
“1” Level
VOH
5.0
15
4.95
14.95
—
—
4.95
14.95
5.0
15
—
—
4.95
14.95
—
—
Vdc
Input Voltage
(VO = 13.5 or 1.5 Vdc)
“0” Level
15
—
4.0
—
6.75
4.0
—
4.0
Vdc
“1” Level
5.0
3.5
—
3.5
2.75
—
3.5
—
Vdc
(VOH = 2.5 Vdc)
Source
Sink
5.0
5.0
15
5.0
– 3.0
– 0.64
– 4.2
0.64
—
—
—
—
– 2.4
– 0.51
– 3.4
0.51
– 4.2
– 0.88
– 8.8
0.88
—
—
—
—
– 1.7
– 0.36
– 2.4
0.36
—
—
—
—
mAdc
Quiescent Current
5.0
—
5.0
—
0.005
5.0
—
150
μ
Adc
(Dynamic plus Quiescent,
buffers switching)
10
IT = (0.60
μ
A/kHz) f + IDD
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in
μ
A (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS
≤
(Vin or Vout)
≤
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
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