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參數(shù)資料
| 型號： | MC14021BFR1 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 計數(shù)移位寄存器 |
| 英文描述： | 4000/14000/40000 SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | EIAJ, PLASTIC, SO-16 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 110K |
| 代理商： | MC14021BFR1 |
MC14014B, MC14021B
http://onsemi.com
4
Characteristic
Symbol
VDD
Vdc
Min
Typ
(Note 6)
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time (Clock to Q, P/S to Q)
tPHL, tPLH = (1.7 ns/pF) CL + 315 ns
tPHL, tPLH = (0.66 ns/pF) CL + 137 ns
tPHL, tPLH = (0.5 ns/pF) CL + 90 ns
tPLH,
tPHL
5.0
10
15
400
170
115
800
340
230
ns
Clock Pulse Width
tWH
5.0
10
15
400
175
135
150
75
40
ns
Clock Frequency
fcl
5.0
10
15
3.0
6.0
8.0
1.5
3.0
4.0
MHz
Parallel/Serial Control Pulse Width
tWH
5.0
10
15
400
175
135
150
75
40
ns
Setup Time
P/S to Clock
tsu
5.0
10
15
200
100
80
100
50
40
ns
Hold Time
Clock to P/S
th
5.0
10
15
20
25
– 2.5
– 10
0
ns
Setup Time
Data (Parallel or Serial) to
Clock or P/S
tsu
5.0
10
15
350
80
60
150
50
30
ns
Hold Time
Clock to Ds
th
5.0
10
15
45
35
0
5
ns
Hold Time
Clock to Pn
th
5.0
10
15
50
45
25
20
ns
Input Clock Rise Time
tr(cl)
5.0
10
15
15
5
4
ms
5. The formulas given are for the typical characteristics only at 25
_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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