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參數(shù)資料
| 型號(hào)： | MC14008BCP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 算術(shù)邏輯單元 |
| 英文描述： | 4000/14000/40000 SERIES, 4-BIT ADDER/SUBTRACTOR, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 255K |
| 代理商： | MC14008BCP |
MOTOROLA CMOS LOGIC DATA
37
MC14008B
4-Bit Full Adder
The MC14008B 4–bit full adder is constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic structure. This
device consists of four full adders with fast internal look–ahead carry output.
It is useful in binary addition and other arithmetic applications. The fast
parallel carry output bit allows high–speed operation when used with other
adders in a system.
Look–Ahead Carry Output
Diode Protection on All Inputs
All Outputs Buffered
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Pin–for–Pin Replacement for CD4008B
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage
– 0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
lin, lout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
PD
Power Dissipation, per Package
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature (8–Second Soldering)
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/
_C From 100_C To 125_C
BLOCK DIAGRAM
HIGH–SPEED
PARALLEL CARRY
14
Cout
13
S4
12
S3
11
S2
10
S1
B4 15
A4
1
B3
2
A3
3
B2
4
A2
5
B1
6
A1
7
Cin
9
ADDER
4
ADDER
3
ADDER
2
ADDER
1
C4
C3
C2
VDD = PIN 16
VSS = PIN 8
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
TRUTH TABLE
(One Stage)
MC14008B
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
Plastic
MC14XXXBCL
Ceramic
MC14XXXBD
SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
S3
S4
Cout
B4
VDD
Cin
S1
S2
B2
A3
B3
A4
VSS
A1
B1
A2
PIN ASSIGNMENT
Cin
B
A
Cout
S
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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