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參數(shù)資料
| 型號(hào)： | MC14006BD |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 18-Bit Static Shift Register |
| 中文描述： | 4000/14000/40000 SERIES, 5-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14 |
| 封裝： | PLASTIC, SOIC-14 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 223K |
| 代理商： | MC14006BD |
MOTOROLA CMOS LOGIC DATA
27
MC14006B
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tPLH, tPHL = (0.5 ns/pF) CL + 55 ns
Clock Pulse Width
10
—
—
50
100
tWH
10
15
5.0
—
—
200
110
80
100
220
160
—
ns
10
15
—
—
8.3
12
4.2
6.0
Clock Pulse Rise and Fall Time**
tTLH
5.0
—
—
15
μ
s
10
15
0
0
– 15
– 8.0
—
—
Hold Time
th
5.0
180
75
—
ns
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**When shift register sections are cascaded, the maximum rise and fall times of the clock input should be equal to or less than the rise and fall times
**
of the data outputs driving data inputs, plus the propagation delay of the output driving stage for the output capacitance load.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS
≤
(Vin or Vout)
≤
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
Figure 1. Typical Output Source Current
Characteristics Test Circuit
Figure 2. Typical Output Sink Current
Characteristics Test Circuit
VDD = –VGS
Vout
14
IOH
EXTERNAL
POWER
SUPPLY
7
VSS
CLOCK Q4
DP1
DP5
DP10
DP14
Q8
Q9
Q13
Q17
Q18
VDD = VGS
Vout
14
IOL
EXTERNAL
POWER
SUPPLY
VSS
CLOCK Q4
DP1
DP5
DP10
DP14
Q8
Q9
Q13
Q17
Q18
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