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參數(shù)資料
| 型號： | MC13109FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Universal Cordless Telephone Subsystem IC |
| 中文描述： | TELECOM, CORDLESS, RF AND BASEBAND CIRCUIT, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 395K |
| 代理商： | MC13109FB |
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MC13109
24
MOTOROLA ANALOG IC DEVICE DATA
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Figure 31. Test Mode Description
TM #
TM 3
value is Divisor (7;2) (the upper 6 bits of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value is Divisor (3;2) (bits 2 and 3
of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) < 2, then output divisor value is (Divisor (3;2) + 60).
TM 2
TM 1
TM 0
Counter Under Test or
Test Mode Option
Input Signal
“Clk Out” Output Expected
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0
0
0
0
0
Normal Operation
>200 mVpp
0 to 2.2 V
–
1
0
0
0
1
Rx Counter, upper 6
Rx Counter, lower 8
Rx Prescaler
Tx Counter, upper 6
Tx Counter, lower 8
Reference Counter
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0 to 2.2 V
Input Frequency/64
2
0
0
1
0
1
See Note Below
3
0
0
1
0
0 to 2.2 V
Input Frequency/4
4
0
1
0
1
0 to 2.2 V
Input Frequency/64
5
0
1
0
0 to 2.2 V
See Note Below
1
1
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1
>200 mVpp
0 to 2.2 V
Input Frequency/4
7
0
1
1
Input Frequency/Reference Counter Value
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0
AGC Gain = 25 Option
0
1
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N/A
–
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Test Modes
Test Mode Control latch bits enable independent testing
of internal counters and set AGC Gain Options. In test
mode, the “Tx VCO” input pin is multiplexed to the input of
the counter under test and the output of the counter under
test is multiplexed to the “Clk Out” output pin so that each
counter can be individually tested. Make sure test mode bits
are set to “0” for normal operation. Test mode operation is
described in Figure 31. During normal operation and when
testing the Tx Prescaler, the “Tx VCO” input can be a
minimum of 200 mVpp at 80 MHz and should be ac coupled.
For other test modes, input signals should be standard logic
levels of 0 to 2.2 V and a maximum frequency of 16 MHz.
Power–Up Defaults for Control and Counter Registers
When the IC is first powered up, all latch registers are
initialized to a defined state. The MC13109 is initially placed in
the Rx mode with all mutes active and nothing disabled. The
reference counter is set to generate a 5.0 kHz reference
frequency from a 10.24 MHz crystal. The MPU clock output
divider is set to 10 to give the minimum clock output frequency.
The Tx and Rx latch registers are set for USA Channel
Frequency #21. Figure 32 shows the initial power–up states
for all latch registers.
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1
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Ref
1
0
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Mode
–
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1
0
0
0
2048
–
–
0
0
1
0
–
0
0
0
0
0
0
1
0
N/A
–
0
–
–
0
0
0
Gain
N/A
–
–
–
–
–
–
–
–
0
–
1
1
0
TM
N/A
–
–
–
–
–
–
–
0
0
0
0
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