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參數(shù)資料
| 型號(hào)： | MC12040P |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | PHASE-FREQUENCY DETECTOR |
| 中文描述： | PHASE DETECTOR, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大?。?/td> | 98K |
| 代理商： | MC12040P |
MC12040
4
MOTOROLA RF/IF DEVICE DATA
APPLICATIONS INFORMATION
The MC12040 is a logic network designed for use as a
phase comparator for MECL–compatible input signals. It
determines the “l(fā)ead” or “l(fā)ag” phase relationship and the time
difference between the leading edges of the waveforms.
Since these edges occur only once per cycle, the detector
has a range of
±
2
π
radians.
Operation of the device may be illustrated by assuming
two waveforms, R and V (Figure 2), of the same frequency
but differing in phase. If the logic had established by past
history that R was leading V, the U output of the detector (pin
4) would produce a positive pulse width equal to the phase
difference and the D output (pin 11 ) would simply remain low.
On the other hand, it is also possible that V was leading R
(Figure 2), giving rise to a positive pulse on the D output and
a constant low level on the U output pin. Both outputs for the
sample condition are valid since the determination of lead or
lag is dependent on past edge crossing and initial conditions
at start–up. A stable phase–locked loop will result from either
condition.
Phase error information is contained in the output duty
cycle–that is, the ratio of the output pulse width to total
period. By integrating or low–pass filtering the outputs of the
detector and shifting the level to accommodate ECL swings,
usable analog information for the voltage controlled oscillator
can be developed. A circuit useful for this function is shown in
Figure 3.
Proper level shifting is accomplished by differentially
driving the operational amplifier from the normally high
outputs of the phase detector (U and D). Using this technique
the quiescent differential voltage to the operational amplifier
is zero (assuming matched “1” levels from the phase
detector). The U and D outputs are then used to pass along
phase information to the operational amplifier. Phase error
summing is accomplished through resistors R1 connected to
the inputs of the operational amplifier. Some R–C filtering
imbedded within the input network (NO TAG) may be very
beneficial since the very narrow correctional pulses of the
MC12040 would not normally be integrated by the amplifier.
Phase detector gain for this configuration is approximately
0.16 volts/radian.
System phase error stems from input offset voltage in the
operational amplifier, mismatching of nominally equal
resistors, and mismatching of phase detector “high” states
between the outputs used for threshold setting and phase
measuring. All these effects are reflected in the gain
constant. For example, a 16mV offset voltage in the amplifier
would cause an error of 0.016/ 0.16 = 0.1 radian or 5.7
degrees of error. Phase error can be trimmed to zero initially
by trimming either input offset or one of the threshold
resistors (R1 in Figure 3). Phase error over temperature
depends on how much the offending parameters drift.
Figure 2. Timing Diagram
Figure 3. Typical Filter and Summing Network
3
510
12
CC
–
+
MC1741
510
CC
R1
2
R1
2
R1
2
R1
2
C
R2
MC12040
U
D
To
VCO
+10 to
+30V
R2
C
R Leads V
(D Output=“0”)
V Leads R
(D Output=“0”)
R
V
Lead
Lag
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