參數(shù)資料
型號(hào)： MC10H189P
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： 3.3V LDO + Dual Switch For USB Peripherals, Active-High Enables 8-MSOP-PowerPAD -40 to 85
中文描述： 10H SERIES, HEX 1-INPUT INVERT GATE, PDIP16
封裝： PLASTIC, DIP-16
文件頁數(shù)： 1/3頁
文件大?。?/td> 97K
代理商： MC10H189P
SEMICONDUCTOR TECHNICAL DATA
2–287
REV 6
Motorola, Inc. 1996
9/96
The MC10H189 is a Hex Inverter with a common Enable input. The hex
inverting function is provided when Enable is in the low–state. When Enable is
in the high–state, all outputs are low.
This MECL 10H part is a functional/pinout duplication of the standard MECL
10K family part, with 100% improvement in propagation delay and no increase
in power–supply current.
Propagation Delay, 1.3 ns Typical Data–to–Output
Power Dissipation 180 mW Typ/Pkg (No Load)
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current— Continuous
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
50
100
Vdc
— Surge
mA
Operating Temperature Range
TA
Tstg
0 to +75
°
C
°
C
°
C
Storage Temperature Range— Plastic
— Ceramic
–55 to +150
–55 to +165
ELECTRICAL CHARACTERISTICS
(VEE = –5.2 V
±
5%) (See Note)
0
°
25
°
75
°
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
IE
IinH
IinL
VOH
VOL
VIH
VIL
—
46
—
42
—
46
mA
μ
A
μ
A
Vdc
Input Current High
—
495
—
310
—
310
Input Current Low
0.5
—
0.5
—
0.3
—
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
High Input Voltage
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
AC PARAMETERS
Propagation Delay
Enable
Data
tpd
0.7
0.7
2.2
1.9
0.7
0.7
2.2
1.9
0.7
0.7
2.3
1.9
ns
Rise Time
tr
tf
0.7
2.4
0.7
2.4
0.7
2.4
ns
Fall Time
0.7
2.4
0.7
2.4
0.7
2.4
ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through
a 50–ohm resistor to –2.0 volts.
LOGIC DIAGRAM
DIP
PIN ASSIGNMENT
12
11
10
7
6
5
9
2
3
4
13
14
15
X
Y
OUT
VCC1
AOUT
BOUT
COUT
AIN
BIN
CIN
VEE
VCC2
FOUT
EOUT
DOUT
FIN
EIN
DIN
COMMON
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
X
L
L
H
H
Y
L
H
L
H
OUT
H
L
L
L
Inputs
Output
VCC1 = Pin 1
VCC2 = Pin 16
VEE = Pin 8
TRUTH TABLE
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
相關(guān)PDF資料
PDF描述
MC10H351FN Quad TTL/NMOS to PECL Translator
MC10H351 Quad TTL/NMOS to PECL Translator
MC10H351L Quad TTL/NMOS to PECL Translator
MC10H351P Quad TTL/NMOS to PECL Translator
MC10H352FN Quad CMOS to PECL* Translator
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