參數(shù)資料
型號： MC10H141FN
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： IC POS V-REG 3-TERM ADJ TO-252
中文描述： 10H SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PQCC20
封裝： PLASTIC, LCC-20
文件頁數(shù)： 1/4頁
文件大?。?/td> 109K
代理商： MC10H141FN
SEMICONDUCTOR TECHNICAL DATA
2–131
REV 6
Motorola, Inc. 1996
9/96
The MC10H141 is a four–bit universal shift register. This device is a
functional/pinout duplication of the standard MECL 10K part with 100%
improvement in propagation delay and operation frequency and no increase in
power supply current.
Shift frequency, 250 MHz Min
Power Dissipation, 425 mW Typical
Improved Noise Margin 150 mV (over operating voltage and
temperature range)
Voltage Compensated
MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current— Continuous
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
50
100
Vdc
— Surge
mA
Operating Temperature Range
TA
Tstg
0 to +75
°
C
°
C
°
C
Storage Temperature Range— Plastic
— Ceramic
–55 to +150
–55 to +165
ELECTRICAL CHARACTERISTICS
(VEE = –5.2 V
±
5%)
0
°
25
°
75
°
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
IE
IinH
—
112
—
102
—
112
mA
μ
A
Input Current High
Pins 5,6,9,11,12,13
Pins 7,10
Pin 4
—
—
—
405
416
510
—
—
—
255
260
320
—
—
—
255
260
320
Input Current Low
IinL
VOH
VOL
VIH
VIL
0.5
—
0.5
—
0.3
—
μ
A
Vdc
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
High Input Voltage
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
AC PARAMETERS
Propagation Delay
tpd
thold
1.0
2.0
1.0
2.0
1.1
2.1
ns
Hold Time —
Data, Select
1.0
—
1.0
—
1.0
—
ns
Set–up Time
Data
Select
tset
1.5
3.0
—
—
1.5
3.0
—
—
1.5
3.0
—
—
ns
Rise Time
tr
tf
0.5
2.4
0.5
2.4
0.5
2.4
ns
Fall Time
0.5
2.4
0.5
2.4
0.5
2.4
ns
Shift Frequency
fshift
250
—
250
—
250
—
MHz
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through
a 50 ohm resistor to –2.0 volts.
L
H
Q2n
32n
H
Parallel Entry
Stop Shift
Q0n
DIP
PIN ASSIGNMENT
VCC1
Q2
Q3
C
DR
D3
S2
VEE
VCC2
Q1
Q0
DL
D0
D1
S1
D2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
TRUTH TABLE
SELECT
OPERATING
MODE
OUTPUTS
S1
S2
Q1n + 1Q2n + 1Q3n + 1
L
L
* Outputs as exist after pulse appears at “C” input with
input conditions as shown (Pulse Positive transition of
clock input).
D0
D1
D2
D3
H
Shift Right*
Q1n
DL
Q2n
Q0n
Q3n
Q1n
DR
H
L
Shift Left*
Q2n
Q1n
Q0n + 1
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
相關(guān)PDF資料
PDF描述
MC10H141 Four-Bit Universal Shift Register
MC10H141L Four-Bit Universal Shift Register
MC10H141P Four-Bit Universal Shift Register
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MC10H600 9-Bit TTL/ECL Translator
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