參數(shù)資料
型號： MC10H131P
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： Dual D Type Master-Slave Flip-Flop
中文描述： 10H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
封裝： PLASTIC, DIP-16
文件頁數(shù)： 1/4頁
文件大?。?/td> 98K
代理商： MC10H131P
SEMICONDUCTOR TECHNICAL DATA
2–69
REV 5
Motorola, Inc. 1996
3/93
The MC10H131 is a MECL 10H part which is a functional/pinout duplication
of the standard MECL 10K family part, with 100% improvement in clock speed
and propagation delay and no increase in power–supply current.
Propagation Delay, 1.0 ns Typical
Power Dissipation, 235 mW Typical
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
50
100
Vdc
— Surge
mA
Operating Temperature Range
TA
Tstg
0 to +75
°
C
°
C
°
C
Storage Temperature Range — Plastic
— Ceramic
–55 to +150
–55 to +165
ELECTRICAL CHARACTERISTICS
(VEE = –5.2 V
±
5%) (See Note)
0
°
25
°
75
°
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
IE
IinH
—
62
—
56
—
62
mA
Input Current High
Pins 6, 11
Pin 9
Pins 7, 10
Pins 4, 5, 12, 13
—
—
—
—
530
660
485
790
—
—
—
—
310
390
285
465
—
—
—
—
310
390
285
465
μ
A
Input Current Low
IinL
VOH
VOL
VIH
VIL
0.5
—
0.5
—
0.3
—
μ
A
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Vdc
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
High Input Voltage
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
AC PARAMETERS
Propagation Delay
Clock, CE
Set, Reset
tpd
0.8
0.6
1.6
1.6
0.8
0.7
1.7
1.7
0.8
0.7
1.8
1.8
ns
Rise Time
tr
tf
0.6
2.0
0.6
2.0
0.6
2.2
ns
Fall Time
0.6
2.0
0.6
2.0
0.6
2.2
ns
Set–up Time
tset
thold
ftog
0.7
—
0.7
—
0.7
—
ns
Hold Time
0.8
—
0.8
—
0.8
—
ns
Toggle Frequency
250
—
250
—
250
—
MHz
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through
a 50–ohm resistor to –2.0 volts.
LOGIC DIAGRAM
DIP
PIN ASSIGNMENT
VCC1
Q1
Q1
R1
S1
CE1
D1
VEE
VCC2
Q2
Q2
R2
S2
CE2
D2
CC
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
S1 5
D1 7
CE1 6
R1 4
CC 9
R2 13
CE2 11
D2 10
S2 12
Q1
Q1
Q2
Q2
2
3
14
15
CLOCKED TRUTH TABLE
N.D. = Not Defined
C = CE + CC
A clock H is a clock transition
from a low to a high state.
RS TRUTH TABLE
R
S
Qn+1
Qn
H
L
N.D.
L
L
H
H
L
H
L
H
C
D
Qn+1
Qn
L
H
L
H
H
X
L
H
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
相關(guān)PDF資料
PDF描述
MC10H131 Dual In/Single Out Autoswitching Power MUX, Manual/Auto Sw, Adj. Cur Limit, Adj. Vol Threshold 8-TSSOP -40 to 85
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