參數(shù)資料
型號(hào)： MC10H116L
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： 16 MEGABIT 3.3 VOLT SERIAL CONFIGURATION - NOT RECOMMENDED for NEW DESIGN
中文描述： TRIPLE LINE RECEIVER, CDIP16
封裝： CERAMIC, DIP-16
文件頁數(shù)： 1/4頁
文件大?。?/td> 110K
代理商： MC10H116L
SEMICONDUCTOR TECHNICAL DATA
2–219
REV 6
Motorola, Inc. 1996
9/96
The MC10H116 is a functional/pinout duplication of the MC10116, with 100%
improvement in propagation delay and no increase in power– supply current.
Propagation Delay, 1.0 ns Typical
Power Dissipation 85 mW Typ/Pkg (same as MECL 10K)
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
50
100
Vdc
— Surge
mA
Operating Temperature Range
TA
Tstg
0 to +75
°
C
°
C
°
C
Storage Temperature Range — Plastic
— Ceramic
–55 to +150
–55 to +165
ELECTRICAL CHARACTERISTICS
(VEE = –5.2 V
±
5%) (2)
0
°
25
°
75
°
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
IE
IinH
ICBO
VBB
VOH
VOL
VIH
VIL
VCMR
—
23
—
21
—
23
mA
Input Current High
—
150
—
95
—
95
μ
A
μ
A
Input Leakage Current
—
1.5
—
1.0
—
1.0
Reference Voltage
–1.38
–1.27
–1.35
–1.25
–1.31
–1.19
Vdc
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Vdc
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
High Input Voltage (1)
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage (1)
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
Common Mode
Range (3)
—
—
–2.85 to –0.8
—
—
Vdc
Input Sensitivity (4)
VPP
—
—
150 typ
—
—
mVPP
AC PARAMETERS
Propagation Delay
tpd
tr
tf
0.4
1.3
0.4
1.3
0.45
1.45
ns
Rise Time
0.5
1.5
0.5
1.6
0.5
1.7
ns
Fall Time
0.5
1.5
0.5
1.6
0.5
1.7
ns
NOTES:
1. When VBB is used as the reference voltage.
2. Each MECL 10H series circuit has been designed to meet the specifications shown in the test table, after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse
air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.
3. Differential input not to exceed 1.0 Vdc.
4. 150 mVp–p differential input required to obtain full logic swing on output.
LOGIC DIAGRAM
DIP PIN ASSIGNMENT
VCC1
AOUT
AOUT
AIN
AIN
BOUT
BOUT
VEE
VCC2
COUT
COUT
CIN
CIN
VBB
BIN
BIN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
5
4
11
3
2
10
9
7
6
13
12
15
14
*and bypassed (when used) with 0.01
μ
F to 0.1
μ
F
cThe MC10H116 is designed to be used in sensing
differential signals over long lines. The bias supply
(VBB) is made available to make the device useful as a
reference voltage is necessary.
Active current sources provide these receivers with
excellent common–mode noise rejection. If any amplifi-
er in a package is not used, one input of that amplifier
must be connected to VBB to prevent unbalancing the
The MC10H116 does not have internal–input pull-
down resistors. This provides high impedance to the
amplifier input and facilitates differential connections.
Applications:
Low Level Receiver
Schmitt Trigger
Voltage Level
Interface
When input pin with
bubble goes positive
it’s respective output
pin with bubble goes
positive.
VCC1 = Pin 1
VCC2 = Pin 16
VEE = Pin 8
VBB*
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
D SUFFIX
PLASTIC SOIC
CASE 751B–05
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
相關(guān)PDF資料
PDF描述
MC10H116P 16 MEGABIT 3.3 VOLT SERIAL CONFIGURATION - NOT RECOMMENDED for NEW DESIGN
MC10H117FN Dual 2-Wide 2-3-input OR-AND/OR-AND Gate
MC10H117 Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate
MC10H117L 1MB 3.3 VOLT ISP CONFIGURATION PROM
MC10H117P Dual 2-Wide 2-3-input OR-AND/OR-AND Gate
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