參數(shù)資料
型號： MC10H016L
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： 4-Bit Binary Counter
中文描述： 10H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16
封裝： CERAMIC, DIP-16
文件頁數(shù)： 1/4頁
文件大?。?/td> 140K
代理商： MC10H016L
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 6
Motorola, Inc. 1996
9/96
The MC10H016 is a high–speed synchronous, presettable, cascadable
4–bit binary counter. It is useful for a large number of conversion, counting and
digital integration applications.
Counting Frequency, 200 MHz Minimum
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K–Compatible
Positive Edge Triggered
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
50
100
Vdc
— Surge
mA
Operating Temperature Range
TA
Tstg
0 to +75
°
C
°
C
Storage Temperature Range — Plastic
— Ceramic
–55 to +150
–55 to +165
ELECTRICAL CHARACTERISTICS
(VEE = –5.2 V
±
5%) (See Note)
0
°
25
°
75
°
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
IE
IinH
—
126
—
115
—
126
mA
Input Current High
All Except MR
Pin 12 MR
—
—
450
1190
—
—
265
700
—
—
265
700
μ
A
Input Current Low
IinL
VOH
VOL
VIH
VIL
0.5
—
0.5
—
0.3
—
μ
A
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Vdc
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
High Input Voltage
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
AC PARAMETERS
Propagation Delay
Clock to Q
Clock to TC
MR to Q
tpd
1.0
0.7
0.7
2.4
2.4
2.4
1.0
0.7
0.7
2.5
2.5
2.5
1.0
0.7
0.7
2.7
2.6
2.6
ns
Set–up Time
Pn to Clock
CE or PE to Clock
tset
2.0
2.5
—
—
2.0
2.5
—
—
2.0
2.5
—
—
ns
Hold Time
Clock to Pn
Clock to CE or PE
thold
1.0
0.5
—
—
1.0
0.5
—
—
1.0
0.5
—
—
ns
Counting Frequency
fcount
tr
tf
200
—
200
—
200
—
MHz
Rise Time
0.5
2.0
0.5
2.1
0.5
2.2
ns
Fall Time
0.5
2.0
0.5
2.1
0.5
2.2
ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a
50–ohm resistor to –2.0 volts.
DIP
PIN ASSIGNMENT
VCC1
Q1
Q0
TC
PE
CE
PO
VEE
VCC2
Q2
Q3
CP
MR
P3
P2
P1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
TRUTH TABLE
CE
PE
MR
CP
Function
L
H
L
H
X
X
L
L
H
H
X
X
L
L
L
L
L
H
Z
Z
Z
Z
ZZ
X
Load Parallel (Pn to Qn)
Load Parallel (Pn to Qn)
Count
Hold
Masters Respond;
Slaves Hold
Reset (Qn = LOW,
TC = HIGH)
Z = Clock Pulse (Low to High);ZZ = Clock Pulse (High to Low)
Features include assertion inputs and outputs on each
of the four master/slave counting flip–flops. Terminal
count is generated internally in a manner that allows
synchronous loading at nearly the speed of the basic
counter.
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
相關(guān)PDF資料
PDF描述
MC10H016P 4-Bit Binary Counter
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