MC10EP35, MC100EP35
http://onsemi.com
2
1
2
3
45
6
7
8
Q
VEE
VCC
Figure 1. 8Lead Pinout (Top View) and Logic Diagram
K
Q
CLK
RESET
J
K
R
Flip Flop
Table 1. PIN DESCRIPTION
PIN
CLK*
J*, K*
ECL Signal Inputs
FUNCTION
ECL Clock Inputs
RESET*
ECL Asynchronous Reset
Q, Q
ECL Data Outputs
Table 2. TRUTH TABLE
J
L
H
X
K
L-
H
L
H
X
RESET
L
H
CLK
Z
X
Qn+1
Qn
L
H
Qn
L
Z = LOW to HIGH Transition
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
EP
(DFN8 only) Thermal exposed pad must be
connected to a sufficient thermal conduit.
Electrically connect to the most negative
supply (GND) or leave unconnected, float-
ing open.
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note
1)Pb Pkg
PbFree Pkg
SOIC8
TSSOP8
DFN8
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL94 V0 @ 0.125 in
Transistor Count
77 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.