參數(shù)資料
型號: MC10EP16VC
廠商: ON SEMICONDUCTOR
英文描述: 3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output(3.3V / 5V ECL差分收發(fā)器(帶高增益和使能輸出))
中文描述: 3.3 / 5V的ECL差分接收器/高增益和啟用輸出電壓(3.3V / 5V的ECL差分收發(fā)器驅(qū)動器(帶高增益和使能輸出))
文件頁數(shù): 1/8頁
文件大?。?/td> 79K
代理商: MC10EP16VC
Semiconductor Components Industries, LLC, 2001
February, 2001 – Rev. 0
1
Publication Order Number:
MC10EP16VC/D
MC10EP16VC, MC100EP16VC
Product Preview
3.3V / 5VECL Differential
Receiver/Driver with High
Gain and Enable Output
The EP16VC is a world–class differential receiver/driver. The device is
functionally equivalent to the EP16 and LVEP16 devices but with high
gain and enable output.
The EP16VC provides an EN input which is synchronized with the
data input (D) signal in a way that provides glitchless gating of the QHG
and QHG outputs.
When the EN signal is LOW, the input is passed to the outputs and the
data output equals the data input. When the data input is HIGH and EN
goes HIGH, it will force the Q
HG
LOW and the Q
HG
HIGH on the next
negative transition of the data input. If the data input is LOW when the
EN goes HIGH, the next data transition to a HIGH is ignored and Q
HG
remains LOW and Q
HG
remains HIGH. The next positive transition of
the data input is not passed on to the data outputs under these conditions.
The Q
HG
and Q
HG
outputs remain in their disabled state as long as the
EN input is held HIGH. The EN input has no influence on the Q output
and the data input is passed on (inverted) to this output whether EN is
HIGH or LOW. This configuration is ideal for crystal oscillator
applications where the oscillator can be free running and gated on and off
synchronously without adding extra counts to the output.
The V
BB
pin, an internally generated voltage supply, is available to this
device only. For single-ended input conditions, the unused differential
input is connected to V
BB
as a switching reference voltage. V
BB
may also
rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
F capacitor and limit current sourcing or sinking to 0.5 mA. When not
used, V
BB
should be left open.
Under open input conditions (pulled to V
EE
) internal input clamps will
force the Q output LOW.
The 100 Series contains temperature compensation.
Gain > 200X
300 ps Typical Prop Delay Q, 419 ps Typical Prop Delay QHG, QHG
Maximum Frequency > 3 GHz Typical (See Graph)
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= –3.0 V to –5.5 V
Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D
Q
HG
Output will default LOW with inputs open or at V
EE
ESD Protection: >4 KV HBM, >200 V MM, >2KV CDM
V
BB
Output
New Differential Input Common Mode Range
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count: 167 Devices
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10EP16VCD
SO–8
98 Units/Rail
MC10EP16VCDR2
SO–8
2500 Tape & Reel
MC100EP16VCD
SO–8
98 Units/Rail
MC100EP16VCDR2
SO–8
2500 Tape & Reel
MC10EP16VCDT
TSSOP–8
98 Units/Rail
MC10EP16VCDTR2
TSSOP–8 2500 Tape & Reel
MC100EP16VCDT
TSSOP–8
98 Units/Rail
MC100EP16VCDTR2 TSSOP–8 2500 Tape & Reel
L = Wafer Lot
Y = Year
W= Work Week
*For additional information, see Application Note
AND8002/D
H = MC10
K = MC100
A = Assembly Location
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
1
8
ALYW
HP66
1
8
TSSOP–8
DT SUFFIX
CASE 948R
ALYW
HEP66
1
8
ALYW
KEP66
1
8
1
8
ALYW
KP66
1
8
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