MC10EL32, MC100EL32
http://onsemi.com
2
4
3
Figure 1. Logic Diagram and Pinout Assignment
1
2
5
6
7
8
Q
VEE
VCC
Q
CLK
VBB
R
÷2
Reset
CLK
Table 1. PIN DESCRIPTION
PIN
FUNCTION
CLK, CLK
ECL Clock Inputs*
Reset
ECL Asynch Reset*
Q, Q
ECL Data Outputs
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
EP
(DFN8 only) Thermal exposed pad must be con-
nected to a sufficient thermal conduit. Electric-
ally connect to the most negative supply (GND)
or leave unconnected, floating open.
*Pins will default low when left open.
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI VCC
VI VEE
6
V
Iout
Output Current
Continuous
Surge
50
100
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
40 to +85
°C
Tstg
Storage Temperature Range
65 to +150
°C
qJA
Thermal Resistance (JunctiontoAmbient)
0 lfpm
500 lfpm
SOIC8
190
130
°C/W
qJC
Thermal Resistance (JunctiontoCase)
Standard Board
SOIC8
41 to 44
°C/W
qJA
Thermal Resistance (JunctiontoAmbient)
0 lfpm
500 lfpm
TSSOP8
185
140
°C/W
qJC
Thermal Resistance (JunctiontoCase)
Standard Board
TSSOP8
41 to 44 ± 5%
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
qJA
Thermal Resistance (JunctiontoAmbient)
0 lfpm
500 lfpm
DFN8
129
84
°C/W
Tsol
Wave Solder
Pb
PbFree
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
°C
qJC
Thermal Resistance (JunctiontoCase)
DFN8
35 to 40
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board 2S2P (2 signal, 2 power)