參數(shù)資料
型號: MC10195L
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Hex Inverter/Buffer
中文描述: 10K SERIES, HEX 1-INPUT INVERT GATE, CDIP16
封裝: CERAMIC, DIP-16
文件頁數(shù): 1/4頁
文件大?。?/td> 102K
代理商: MC10195L
SEMICONDUCTOR TECHNICAL DATA
3–164
REV 5
Motorola, Inc. 1996
3/93
The MC10195 is a Hex Buffer Inverter which is built using six EXCLUSIVE
NOR gates. There is a common input to these gates which when placed low or
left open allows them to act as inverters. With the common input connected to
a high logic level the MC10195 is a hex buffer, useful for high fanout clock
driving and reducing stub lengths on long bus lines.
PD= 200 mW typ/pkg (No Load)
tpd= 2.8 ns typ (B–Q)
tpd= 3.8 ns typ (A–Q)
tr, tf= 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1= PIN 1
VCC2= PIN 16
VEE= PIN 8
A
B
9
5
6
7
10
11
12
2
3
4
13
14
15
Q
TRUTH TABLE
Inputs
Output
A
B
Q
L
L
H
L
H
L
H
L
L
H
H
H
DIP
PIN ASSIGNMENT
VCC1
Q1
Q2
Q3
B1
B2
B3
VEE
VCC2
Q6
Q5
Q4
B6
B5
B4
A
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–36 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
相關PDF資料
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