參數(shù)資料
型號(hào): MC10173L
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Quad 2-Input Multiplexer/ Latch
中文描述: 10K SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16
封裝: CERAMIC, DIP-16
文件頁數(shù): 1/5頁
文件大小: 109K
代理商: MC10173L
SEMICONDUCTOR TECHNICAL DATA
3–117
REV 5
Motorola, Inc. 1996
3/93
The MC10173 is a quad two channel multiplexer with latch. It incorporates
common clock and common data select inputs. The select input determines
which data input is enabled. A high (H) level enables data inputs D00, D10,
D20, and D30 and a low (L) level enables data inputs D01, D11, D21, D31. Any
change on the data input will be reflected at the outputs while the clock is low.
The outputs are latched on the positive transition of the clock. While the clock is
in the high state, a change in the information present at the data inputs will not
affect the output information.
PD= 275 mW typ/pkg (No Load)
tpd= 2.5 ns typ
tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
VCC= PIN 16
VEE= PIN 8
1 Q0
2 Q1
15 Q2
14 Q3
SELECT 9
D00 6
D01 5
D10 4
D11 3
D20 13
D21 12
D30 11
D31 10
CLOCK 7
TRUTH TABLE
SELECT
CLOCK
Q0n+1
D00
D01
Q0n
H
L
X
L
L
H
DIP
PIN ASSIGNMENT
Q0
Q1
D11
D10
D01
D00
CLOCK
VEE
VCC
Q2
Q3
D20
D21
D30
D31
SELECT
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
相關(guān)PDF資料
PDF描述
MC10173 Quad 2-Input Multiplexer/Latch
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MC10173P Quad 2-Input Multiplexer/ Latch
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MC10174 Dual 4 to 1 Multiplexer
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