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參數(shù)資料
| 型號(hào)： | MC10161FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 50/30/100-Mhz Presettable Decade OR Binary Counters/Latches 14-CDIP -55 to 125 |
| 中文描述： | 10K SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 120K |
| 代理商： | MC10161FN |
SEMICONDUCTOR TECHNICAL DATA
3–73
REV 5
Motorola, Inc. 1996
3/93
The MC10161 is designed to decode a three bit input word to a one of eight
line output. The selected output will be low while all other outputs will be high. The
enable inputs, when either or both are high, force all outputs high.
The MC10161 is a true parallel decoder. No series gating is used internally,
eliminating unequal delay times found in other decoders. This design provides
the identical 4 ns delay from any address or enable input to any output.
A complete mux/demux operation on 16 bits for data distribution is illustrated
in Figure 1. This system, using the MC10136 control counters, has the
capability of incrementing, decrementing or holding data channels. When both
S0 and S1 are low, the index counters reset, thus initializing both the mux and
demux units. The four binary outputs of the counter are buffered by the
MC10101s to send twisted–pair select data to the multiplexer/demultiplexer to
units.
PD= 315 mW typ/pkg (No Load)
tpd= 4.0 ns typ
tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1= PIN 1
VCC2= PIN 16
VEE= PIN 8
E0 2
E1 15
A 7
B 9
C 14
6 Q0
5 Q1
4 Q2
3 Q3
13 Q4
12 Q5
11 Q6
10 Q7
TRUTH TABLE
ENABLE
INPUTS
INPUTS
OUTPUTS
E1
L
L
L
L
L
L
L
L
H
X
E0
L
L
L
L
L
L
L
L
X
H
C
L
L
L
L
H
H
H
H
X
X
B
L
L
H
H
L
L
H
H
X
X
A
L
H
L
H
L
H
L
H
X
X
Q0
L
H
H
H
H
H
H
H
H
H
Q1
H
L
H
H
H
H
H
H
H
H
Q2
H
H
L
H
H
H
H
H
H
H
Q3
H
H
H
L
H
H
H
H
H
H
Q4
H
H
H
H
L
H
H
H
H
H
Q5
H
H
H
H
H
L
H
H
H
H
Q6
H
H
H
H
H
H
L
H
H
H
Q7
H
H
H
H
H
H
H
L
H
H
DIP
PIN ASSIGNMENT
VCC1
E0
Q3
Q2
Q1
Q0
A
VEE
VCC2
E1
C
Q4
Q5
Q6
Q7
B
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC10161L | 50/30/100-Mhz Presettable Decade OR Binary Counters/Latches 14-CDIP -55 to 125 |
| MC10162 | Binary to 1-8 Decoder(High) |
| MC10162FN | Binary to 1-8 Decoder(High) |
| MC10162L | Binary to 1-8 Decoder(High) |
| MC10162P | Binary to 1-8 Decoder(High) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC10161FN WAF | 制造商:ON Semiconductor 功能描述: |
| MC10161L | 制造商:ON Semiconductor 功能描述:Decoder/Demultiplexer Single 3-to-8 16-Pin CDIP Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10161L1 | 制造商:Motorola Inc 功能描述:Demultiplexer/Decoder, 3 To 8 Line, 16 Pin, Ceramic, DIP |
| MC10161P | 制造商:ON Semiconductor 功能描述:Decoder/Demultiplexer Single 3-to-8 16-Pin PDIP Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10162FN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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