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參數(shù)資料
| 型號(hào)： | MC10138P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-Bit Up/Down Counters (Dual Clock With Clear) 16-CDIP -55 to 125 |
| 中文描述： | 10K SERIES, SYN POSITIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 117K |
| 代理商： | MC10138P |
SEMICONDUCTOR TECHNICAL DATA
3–41
REV 5
Motorola, Inc. 1996
3/93
The MC10138 is a four bit counter capable of divide by two, five, or ten
functions. It is composed of four set–reset master–slave flip–flops. Clock
inputs trigger on the positive going edge of the clock pulse.
Set or reset input override the clock, allowing asynchronous “set” or
“clear.” Individual set and common reset inputs are provided, as well as
complementary outputs for the first and fourth bits.
PD= 370 mW typ/pkg (No Load)
ftog= 150 MHz typ
tr, tf= 2.5 ns typ (20%–80%)
2
LOGIC DIAGRAM
VCC1 = PIN 1; VCC2 = PIN 16; VEE = PIN 8
11
S0
Q0
Q0
14
9
12
Clock
Reset
D1
C1
R
Q
Q
S
15
Q’
10
S1
Q1
D1
C2
R
Q
Q
S
13
Q’
D2
C2
7
6
S2
Q2
D1
C2
R
Q
Q
S
4
Q’
C1
5
S3
Q3
Q3
3
D1
C2
R
Q’
Q
S
Q
D2
COUNTER TRUTH TABLES
BI–QUINARY
(Clock connected to C2
and Q3 connected to C1)
COUNT
Q1
Q2
Q3
0
L
L
L
1
H
L
L
2
L
H
L
3
H
H
L
4
L
L
H
5
L
L
L
6
H
L
L
7
L
H
L
8
H
H
L
9
L
L
H
BCD
(Clock connected to C1
and Q0 connected to C2)
COUNT
Q0
0
L
1
H
2
L
3
H
4
L
5
H
6
L
7
H
8
L
9
H
Q0
L
L
L
L
L
H
H
H
H
H
Q1
L
L
H
H
L
L
H
H
L
L
Q2
L
L
L
L
H
H
H
H
L
L
Q3
L
L
L
L
L
L
L
L
H
H
COUNTER STATE DIAGRAM — POSITIVE LOGIC
0
4
7
1
3
2
6
5
9
8
7
6
5
11
13
12
10
15
14
0
1
2
3
4
CLOCK CONNECTED TO C2
Q0 CONNECTED TO C2
DIP
PIN ASSIGNMENT
VCC1
Q3
Q3
Q2
S3
S2
C2
VEE
VCC2
Q0
Q0
Q1
C1
S0
S1
RESET
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC10141FN | Replaced by SN54LS193 : Synchronous 4-Bit Up/Down Counters (Dual Clock With Clear) 16-CDIP -55 to 125 |
| MC10141 | Synchronous 4-Bit Up/Down Counters (Dual Clock With Clear) 16-CDIP -55 to 125 |
| MC10141 | Four Bit Universal Shift Register |
| MC10141L | Replaced by SN54LS193 : Synchronous 4-Bit Up/Down Counters (Dual Clock With Clear) 16-CDIP -55 to 125 |
| MC10141P | Replaced by SN54LS193 : Synchronous 4-Bit Up/Down Counters (Dual Clock With Clear) 16-CDIP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC10141FN | 制造商:ON Semiconductor 功能描述:Shift Register Single 4-Bit Serial/Parallel to Parallel 20-Pin PLCC Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10141L | 制造商:ON Semiconductor 功能描述:Shift Register Single 4-Bit Serial/Parallel to Parallel 16-Pin CDIP Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10141L WAF | 制造商:ON Semiconductor 功能描述: |
| MC10141LD | 制造商:Motorola Inc 功能描述: |
| MC10141P | 制造商:ON Semiconductor 功能描述:Shift Register Single 4-Bit Serial/Parallel to Parallel 16-Pin PDIP Rail |
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