Table 8. DC CHARACTERISTICS, HSTL VCC
參數(shù)資料
型號: MC100LVEP14DTR2G
廠商: ON Semiconductor
文件頁數(shù): 5/7頁
文件大?。?/td> 0K
描述: IC CLOCK BUFFER MUX 2:5 20-TSSOP
標準包裝: 1
系列: 100LVEP
類型: 扇出緩沖器(分配),多路復用器
電路數(shù): 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 是/是
輸入: ECL,HSTL,LVDS,PECL
輸出: ECL,PECL
頻率 - 最大: 2.5GHz
電源電壓: 2.375 V ~ 3.8 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 標準包裝
其它名稱: MC100LVEP14DTR2GOSDKR
MC100LVEP14
http://onsemi.com
5
Table 8. DC CHARACTERISTICS, HSTL VCC = 2.375 V to 3.8 V, VEE = 0 V
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VIH
Input HIGH Voltage
1200
mV
VIL
Input LOW Voltage
400
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 9. AC CHARACTERISTICS VCC = 0 V, VEE = 2.375 V to 3.8 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 14)
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOUTPP
Output Voltage Amplitude @ 2.5 GHz
(Figure 2)
330
425
280
375
230
295
mV
tPLH
tPHL
Propagation Delay to
Output Differential
300
375
425
300
400
475
300
430
525
ps
tskew
WithinDevice Skew (Note 15)
DevicetoDevice Skew (Note 15)
10
100
25
125
15
150
25
175
15
200
25
225
ps
ts
th
Setup Time
EN
Hold Time
EN
100
200
50
140
100
200
50
140
100
200
50
140
ps
tJITTER
CLOCK Random Jitter (RMS)
@ v 1.0 GHz
@ v 1.5 GHz
@ v 2.0 GHz
@ v 2.5 GHz
0.157
0.163
0.180
0.179
0.3
0.2
0.3
0.181
0.176
0.201
0.208
0.3
0.212
0.218
0.235
0.253
0.3
0.4
ps
VPP
Minimum Input Swing
150
800
1200
150
800
1200
150
800
1200
mV
tr/tf
Output Rise/Fall Time (20%80%)
125
165
225
125
180
250
125
200
275
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V.
15.Skew is measured between outputs under identical transitions.
Resource Reference of Application Notes
AN1405/D
ECL Clock Distribution Techniques
AN1406/D
Designing with PECL (ECL at +5.0 V)
AN1503/D
ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
Metastability and the ECLinPS Family
AN1568/D
Interfacing Between LVDS and ECL
AN1672/D
The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
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