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參數(shù)資料
| 型號(hào)： | MC100LVEP14DTR2 |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:5 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | 100LVEP |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | ECL，HSTL，LVDS，PECL |
| 輸出： | ECL，PECL |
| 頻率 - 最大： | 2.5GHz |
| 電源電壓： | 2.375 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2010
June, 2010 Rev. 13
1
Publication Order Number:
MC100LVEP14/D
MC100LVEP14
2.5V / 3.3V1:5 Differential
ECL/PECL/HSTL Clock Driver
Description
The MC100LVEP14 is a low skew 1to5 differential driver, designed
with clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
singleended (if the VBB output is used). HSTL inputs can be used when
the LVEP14 is operating under PECL conditions.
The LVEP14 specifically guarantees low outputtooutput skew.
Optimal design, layout, and processing minimize skew within a device and
from device to device.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated identically into 50
W
even if only one output is being used. If an output pair is unused, both
outputs may be left open (unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock; therefore, all associated specification limits are referenced to
the negative edge of the clock input.
The MC100LVEP14, as with most other ECL devices, can be
operated from a positive VCC supply in PECL mode. This allows the
LVEP14 to be used for high performance clock distribution in +3.3 V
or +2.5 V systems. Singleended CLK input pin operation is limited to
a VCC ≥ 3.0 V in PECL mode, or VEE ≤ 3.0 V in NECL mode.
Designers can take advantage of the LVEP14’s performance to
distribute low skew clocks across the backplane or the board.
Features
100 ps DevicetoDevice Skew
25 ps Within Device Skew
400 ps Typical Propagation Delay
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode:
VCC = 2.375 V to 3.8 V with VEE = 0 V
NECL Mode:
VCC = 0 V with VEE = 2.375 V to 3.8 V
LVDS Input Compatible
Open Input Default State
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
TSSOP20
DT SUFFIX
CASE 948E
MARKING DIAGRAM*
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
100
VP14
ALYWG
1
20
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
G
(Note: Microdot may be in either location)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100LVEP14DTR2G | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 2.5V/3.3V 1:5 Diff ECL/PECL/HST Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100LVEP16D | 功能描述:總線收發(fā)器 2.5V/3.3V ECL Diff RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| MC100LVEP16DG | 功能描述:總線收發(fā)器 2.5V/3.3V ECL Diff RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| MC100LVEP16DR2 | 功能描述:總線收發(fā)器 2.5V/3.3V ECL Diff RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| MC100LVEP16DR2G | 功能描述:總線收發(fā)器 2.5V/3.3V ECL Diff RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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